aboutsummaryrefslogtreecommitdiff
path: root/include/llvm/CodeGen
AgeCommit message (Expand)Author
2012-11-13Merge commit 'be02a90de17f857ba65bbd8a11653ca1bad30adc'Derek Schuff
2012-11-14Use TARGET2 relocation for TType references on ARM.Anton Korobeynikov
2012-11-13misched: Don't consider artificial edges weak edges.Andrew Trick
2012-11-12misched: Target-independent support for load/store clustering.Andrew Trick
2012-11-12misched: Infrastructure for weak DAG edges.Andrew Trick
2012-11-08Add @nacl.read.tp() intrinsic, a fast version of NaCl's tls_get() IRT interfaceMark Seaborn
2012-11-07misched: Heuristics based on the machine model.Andrew Trick
2012-11-07misched: handle on-the-fly regpressure queries better for 2-addrAndrew Trick
2012-11-06Merge commit 'cfe09ed28d8a65b671e8b7a716a933e98e810e32'Derek Schuff
2012-11-06misched: TargetSchedule interface for machine resources.Andrew Trick
2012-11-06ScheduleDAG interface. Added OrderKind to distinguish nonregister dependencies.Andrew Trick
2012-10-31Add extra declarations of hash_value needed to build llvm with xlc 12.1.Rafael Espindola
2012-10-30[inline asm] Get the mayLoad/mayStore directly from the MIOp_ExtraInfo operand.Chad Rosier
2012-10-30[inline asm] Implement mayLoad and mayStore for inline assembly. In general,Chad Rosier
2012-10-29In various places throughout the code generator, there were specialUlrich Weigand
2012-10-26Remove GC roots that reference dead objects.Nicolas Geoffray
2012-10-25Merge commit 'a8a0a155de16830b8fcab539ba2ec21de3145532'Derek Schuff
2012-10-23Merge commit '92b0d8cf2c51debc7f4fb30a417ae839077a8ed0'Derek Schuff
2012-10-23Use ilist rather than std::list for Node and Edge lists in the PBQP graph. ThisLang Hames
2012-10-18Reapply the TargerTransformInfo changes, minus the changes to LSR and Lowerin...Nadav Rotem
2012-10-18Merge commit '3298959540ca744ec16b4c65db244534a929a862'Derek Schuff
2012-10-18Change MachineFrameInfo::StackObject::Alloca from Value* to AllocaInst*Sebastian Pop
2012-10-18Temporarily revert the TargetTransform changes.Bob Wilson
2012-10-17Switch MRI::UsedPhysRegs to a register unit bit vector.Jakob Stoklund Olesen
2012-10-17Add a really faster pre-RA scheduler (-pre-RA-sched=linearize). It doesn't useEvan Cheng
2012-10-17Merge MRI::isPhysRegOrOverlapUsed() into isPhysRegUsed().Jakob Stoklund Olesen
2012-10-17Use a SparseSet instead of a BitVector for UsedInInstr in RAFast.Jakob Stoklund Olesen
2012-10-16Merge commit '320db3f8052c9f506d9ea043ba5da534df40aa08'Derek Schuff
2012-10-16Fix function parameter spelling in comments. Caught by -Wdocumentation.Dmitri Gribenko
2012-10-16misched: Added handleMove support for updating all kill flags, not just for a...Andrew Trick
2012-10-15Remove RegisterClassInfo::isReserved() and isAllocatable().Jakob Stoklund Olesen
2012-10-15Remove LIS::isAllocatable() and isReserved() helpers.Jakob Stoklund Olesen
2012-10-15Switch most getReservedRegs() clients to the MRI equivalent.Jakob Stoklund Olesen
2012-10-15Freeze the reserved registers as soon as isel is complete.Jakob Stoklund Olesen
2012-10-15Merge commit 'bb20b24224734f5369d124181d086703ca439dd7'Derek Schuff
2012-10-15misched: ILP scheduler for experimental heuristics.Andrew Trick
2012-10-12Merge commit '40573998821fde7ffeabe8507f4c9e8c7cf762f6'Derek Schuff
2012-10-11Merge commit '2fa8af224ea026f9432e833fd6f42a216423a010'Derek Schuff
2012-10-11Remove unnecessary classof()'sSean Silva
2012-10-11Change MachineInstrBuilder::addDisp to copy over target flags by default.Evan Cheng
2012-10-10Add a new interface to allow IR-level passes to access codegen-specific infor...Nadav Rotem
2012-10-10misched: Use the TargetSchedModel interface wherever possible.Andrew Trick
2012-10-09misched: Add computeInstrLatency to TargetSchedModel.Andrew Trick
2012-10-09misched: Doxument the TargetSchedule API.Andrew Trick
2012-10-09misched: Allow flags to disable hasInstrSchedModel/hasInstrItineraries for ex...Andrew Trick
2012-10-09misched: Remove LoopDependencies heuristic.Andrew Trick
2012-10-09Add in some interfaces that will allow easier access to the pointer address s...Micah Villmow
2012-10-08misched: remove forceUnitLatencies. Defaults are handled by the default Sched...Andrew Trick
2012-10-08Move TargetData to DataLayout.Micah Villmow
2012-10-07Remove unused MachineInstr constructors that don't take a DebugLoc argument.Craig Topper
generated by cgit v1.2.3-70-g09d2 (git 2.46.0) at 2025-12-27 06:15:39 +0000