emscripten-fastcomp - LLVM with the emscripten fastcomp javascript backend

Age	Commit message (Expand)	Author
2013-04-13	MI-Sched: schedule physreg copies.	Andrew Trick
2013-03-01	Fix incorrect ScheduleDAG comment and formalize Weak edges.	Andrew Trick
2013-02-20	Fix #includes, so we include only what we really need.	Jakub Staszak
2013-01-25	MachineScheduler support for viewGraph.	Andrew Trick
2013-01-25	ScheduleDAG: Added isBoundaryNode to conveniently detect a common corner case.	Andrew Trick
2013-01-24	MIsched: Added biasCriticalPath.	Andrew Trick
2012-12-03	Sort the #include lines for the include/... tree with the script.	Chandler Carruth
2012-11-13	misched: Don't consider artificial edges weak edges.	Andrew Trick
2012-11-12	misched: Infrastructure for weak DAG edges.	Andrew Trick
2012-11-06	misched: TargetSchedule interface for machine resources.	Andrew Trick
2012-11-06	ScheduleDAG interface. Added OrderKind to distinguish nonregister dependencies.	Andrew Trick
2012-10-10	misched: Use the TargetSchedModel interface wherever possible.	Andrew Trick
2012-10-08	misched: remove forceUnitLatencies. Defaults are handled by the default Sched...	Andrew Trick
2012-08-23	Simplify the computeOperandLatency API.	Andrew Trick
2012-06-13	sched: Avoid trivially redundant DAG edges. Take the one with higher latency.	Andrew Trick
2012-06-05	misched: API for minimum vs. expected latency.	Andrew Trick
2012-03-14	misched: implemented a framework for top-down or bottom-up scheduling.	Andrew Trick
2012-03-07	misched preparation: rename core scheduler methods for consistency.	Andrew Trick
2012-03-07	misched preparation: clarify ScheduleDAG and ScheduleDAGInstrs roles.	Andrew Trick
2012-03-07	misched preparation: modularize schedule emission.	Andrew Trick
2012-03-07	misched preparation: modularize schedule printing.	Andrew Trick
2012-03-07	misched preparation: modularize schedule verification.	Andrew Trick
2012-03-07	Cleanup in preparation for misched: Move DAG visualization logic.	Andrew Trick
2012-03-07	Cleanup: DAG building is specific to either SD or MI scheduling. Not part of ...	Andrew Trick
2012-03-07	misched comments	Andrew Trick
2012-02-22	Initialize SUnits before DAG building.	Andrew Trick
2012-02-06	Move some llvm_unreachable's from r149849 out of switch statements to satisfy...	Craig Topper
2012-02-05	Convert assert(0) to llvm_unreachable	Craig Topper
2012-01-12	Move Sched::Preference out of TargetMachine.h where it is not referenced.	Evan Cheng
2011-12-20	Unweaken vtables as per http://llvm.org/docs/CodingStandards.html#ll_virtual_...	David Blaikie
2011-06-28	- Rename TargetInstrDesc, TargetOperandInfo to MCInstrDesc and MCOperandInfo and	Evan Cheng
2011-06-15	Added -stress-sched flag in the Asserts build.	Andrew Trick
2011-06-02	Remove dead code.	Devang Patel
2011-04-26	Be careful about scheduling nodes above previous calls. It increase usages of	Evan Cheng
2011-04-15	Fix a ton of comment typos found by codespell. Patch by	Chris Lattner
2011-04-14	In the pre-RA scheduler, maintain cmp+br proximity.	Andrew Trick
2011-04-07	Added a check in the preRA scheduler for potential interference on a	Andrew Trick
2011-03-07	Typos.	Eric Christopher
2011-02-04	Introducing a new method of tracking register pressure. We can't	Andrew Trick
2010-12-25	Header warning patrol.	Eric Christopher
2010-12-24	Minor cleanup related to my latest scheduler changes.	Andrew Trick
2010-12-24	Various bits of framework needed for precise machine-level selection	Andrew Trick
2010-12-24	whitespace	Andrew Trick
2010-12-20	update comment.	Chris Lattner
2010-11-25	SDep is POD-like. Shave off a few bytes from SUnit by moving a member around.	Benjamin Kramer
2010-11-03	Two sets of changes. Sorry they are intermingled.	Evan Cheng
2010-05-26	Change push_all to a non-virtual function and implement it in the	Dan Gohman
2010-05-26	Delete an unused function.	Dan Gohman
2010-05-20	Allow targets more controls on what nodes are scheduled by reg pressure, what...	Evan Cheng
2010-05-20	Add a hybrid bottom up scheduler that reduce register usage while avoiding	Evan Cheng