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path: root/include/llvm/CodeGen/MachineRegisterInfo.h
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2010-05-11Simplify the tracking of used physregs to a bulk bitor followed by a transitiveJakob Stoklund Olesen
closure after allocating all blocks. Add a few more test cases for -regalloc=fast. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103500 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-28Replace r102368 with code that's less fragile. This creates DBG_VALUE ↵Evan Cheng
instructions for function arguments early and insert them after instruction selection is done. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102554 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-14Move the code for emitting livein copies out of SelectionDAGISel.Dan Gohman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101254 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-13Move MachineRegisterInfo's isLiveIn and isLiveOut out of line.Dan Gohman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101145 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-03Add MachineRegisterInfo::hasOneUse and hasOneNonDBGUse.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97663 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-06Add a Debug bit to MachineOperand, for uses thatDale Johannesen
are from debug info. Add an iterator to MachineRegisterInfo to skip Debug operands when walking the use list. No functional change yet. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95473 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-09Print "..." instead of all the uninteresting register clobbers on callDan Gohman
instructions. This makes CodeGen dumps significantly less noisy. Example before: BL <ga:@bar>, %R0<imp-def>, %R1<imp-def,dead>, %R2<imp-def,dead>, %R3<imp-def,dead>, %R12<imp-def,dead>, %LR<imp-def,dead>, %D0<imp-def,dead>, %D1<imp-def,dead>, %D2<imp-def,dead>, %D3<imp-def,dead>, %D4<imp-def,dead>, %D5<imp-def,dead>, %D6<imp-def,dead>, %D7<imp-def,dead>, %D16<imp-def,dead>, %D17<imp-def,dead>, %D18<imp-def,dead>, %D19<imp-def,dead>, %D20<imp-def,dead>, %D21<imp-def,dead>, %D22<imp-def,dead>, %D23<imp-def,dead>, %D24<imp-def,dead>, %D25<imp-def,dead>, %D26<imp-def,dead>, %D27<imp-def,dead>, %D28<imp-def,dead>, %D29<imp-def,dead>, %D30<imp-def,dead>, %D31<imp-def,dead>, %CPSR<imp-def,dead>, %FPSCR<imp-def,dead> Same example after: BL <ga:@bar>, %R0<imp-def>, %R1<imp-def,dead>, %LR<imp-def,dead>, %CPSR<imp-def,dead>, ... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86583 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-27eliminate all 80-col violations that I have introduced in my recent checkins ↵Gabor Greif
(and some others more) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80304 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-27Clean up the minor mess I caused with removing iterator.h. I shall take care ↵Gabor Greif
of 80-col violations and the FIXME later. (Thanks goodness that I live in another continent, so the monkeypox did not strike me :-) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80224 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-15Part 1.Evan Cheng
- Change register allocation hint to a pair of unsigned integers. The hint type is zero (which means prefer the register specified as second part of the pair) or entirely target dependent. - Allow targets to specify alternative register allocation orders based on allocation hint. Part 2. - Use the register allocation hint system to implement more aggressive load / store multiple formation. - Aggressively form LDRD / STRD. These are formed *before* register allocation. It has to be done this way to shorten live interval of base and offset registers. e.g. v1025 = LDR v1024, 0 v1026 = LDR v1024, 0 => v1025,v1026 = LDRD v1024, 0 If this transformation isn't done before allocation, v1024 will overlap v1025 which means it more difficult to allocate a register pair. - Even with the register allocation hint, it may not be possible to get the desired allocation. In that case, the post-allocation load / store multiple pass must fix the ldrd / strd instructions. They can either become ldm / stm instructions or back to a pair of ldr / str instructions. This is work in progress, not yet enabled. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73381 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-14Move register allocation preference (or hint) from LiveInterval to ↵Evan Cheng
MachineRegisterInfo. This allows more passes to set them. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73346 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-15Move MachineRegisterInfo::setRegClass out of line.Dan Gohman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69126 91177308-0d34-0410-b5e6-96231b3b80d8
2009-01-07Add empty() methods for register def lists.Dan Gohman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61890 91177308-0d34-0410-b5e6-96231b3b80d8
2008-12-08Move createVirtualRegister out-of-line.Dan Gohman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60684 91177308-0d34-0410-b5e6-96231b3b80d8
2008-10-20Add a register class -> virtual registers map.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57844 91177308-0d34-0410-b5e6-96231b3b80d8
2008-07-25Enable rematerialization of constants using ↵Dan Gohman
AliasAnalysis::pointsToConstantMemory, and knowledge of PseudoSourceValues. This unfortunately isn't sufficient to allow constants to be rematerialized in PIC mode -- the extra indirection is a complication. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54000 91177308-0d34-0410-b5e6-96231b3b80d8
2008-06-19Minor spiller tweak to unfavor reload into load/store instructions.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52477 91177308-0d34-0410-b5e6-96231b3b80d8
2008-06-18Add MachineRegisterInfo::use_empty.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52451 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-29For PR1338: rename include/llvm/ADT/ilist and friends to end with ".h"Anton Korobeynikov
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51687 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-05Fix more -Wshorten-64-to-32 warnings.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50659 91177308-0d34-0410-b5e6-96231b3b80d8
2008-04-01update comment.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49010 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-20Unbreak build with gcc 4.3: provide missed includes and silence most ↵Anton Korobeynikov
annoying warnings. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47367 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-13Added debugging routine dumpUses.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47042 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-10Rename MRegisterInfo to TargetRegisterInfo.Dan Gohman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46930 91177308-0d34-0410-b5e6-96231b3b80d8
2008-01-29Add explicit keywords.Dan Gohman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46506 91177308-0d34-0410-b5e6-96231b3b80d8
2008-01-10provide def_* and use_* iterators in addition to reg_* iterators.Chris Lattner
The first only returns definitions of a register, the second only returns uses, the third returns both. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45803 91177308-0d34-0410-b5e6-96231b3b80d8
2008-01-03don't access element zero of an array of size zero.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45526 91177308-0d34-0410-b5e6-96231b3b80d8
2008-01-01switch the register iterator to act more like hte LLVM value iterator: ↵Chris Lattner
dereferencing it now returns the machineinstr of the use. To get the operand, use I.getOperand(). Add a new MachineRegisterInfo::replaceRegWith, which is basically like Value::replaceAllUsesWith. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45482 91177308-0d34-0410-b5e6-96231b3b80d8
2008-01-01Add a trivial but handy function to efficiently return the machine Chris Lattner
instruction that defines the specified vreg. Crazy. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45480 91177308-0d34-0410-b5e6-96231b3b80d8
2008-01-01add efficient iteration support for register use/def's Chris Lattner
within a machine function. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45479 91177308-0d34-0410-b5e6-96231b3b80d8
2008-01-01Implement automatically updated def/use lists for all MachineInstr register Chris Lattner
operands. The lists are currently kept in MachineRegisterInfo, but it does not yet provide an iterator interface to them. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45477 91177308-0d34-0410-b5e6-96231b3b80d8
2007-12-31Rename SSARegMap -> MachineRegisterInfo in keeping with the idea Chris Lattner
that "machine" classes are used to represent the current state of the code being compiled. Given this expanded name, we can start moving other stuff into it. For now, move the UsedPhysRegs and LiveIn/LoveOuts vectors from MachineFunction into it. Update all the clients to match. This also reduces some needless #includes, such as MachineModuleInfo from MachineFunction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45467 91177308-0d34-0410-b5e6-96231b3b80d8
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