diff options
Diffstat (limited to 'test')
| -rw-r--r-- | test/NaCl/Bitcode/intrinsic-pointer-args.ll | 55 |
1 files changed, 55 insertions, 0 deletions
diff --git a/test/NaCl/Bitcode/intrinsic-pointer-args.ll b/test/NaCl/Bitcode/intrinsic-pointer-args.ll new file mode 100644 index 0000000000..0848568fd3 --- /dev/null +++ b/test/NaCl/Bitcode/intrinsic-pointer-args.ll @@ -0,0 +1,55 @@ +; Test that intrinsic declarations are read back correctly. + +; RUN: llvm-as < %s | pnacl-freeze --pnacl-version=1 | pnacl-thaw \ +; RUN: | llvm-dis - | FileCheck %s -check-prefix=TD + +; RUN: llvm-as < %s | pnacl-freeze --pnacl-version=2 | pnacl-thaw \ +; RUN: | llvm-dis - | FileCheck %s -check-prefix=TD + + +declare i8* @llvm.stacksave() +declare void @llvm.stackrestore(i8*) + +declare i8* @llvm.nacl.read.tp() +declare void @llvm.nacl.longjmp(i8*, i32) +declare void @llvm.nacl.setjmp(i8*) + +declare void @llvm.memcpy.p0i8.p0i8.i32(i8* nocapture, i8* nocapture, i32, i32, i1) +declare void @llvm.memmove.p0i8.p0i8.i32(i8* nocapture, i8* nocapture, i32, i32, i1) +declare void @llvm.memset.p0i8.i32(i8* nocapture, i8, i32, i32, i1) + +declare i32 @llvm.nacl.atomic.load.i32(i32*, i32) +declare i64 @llvm.nacl.atomic.load.i64(i64*, i32) + +declare i32 @llvm.nacl.atomic.cmpxchg.i32(i32*, i32, i32, i32, i32) +declare i64 @llvm.nacl.atomic.cmpxchg.i64(i64*, i64, i64, i32, i32) + +declare void @llvm.nacl.atomic.store.i32(i32, i32*, i32) +declare void @llvm.nacl.atomic.store.i64(i64, i64*, i32) + +declare i32 @llvm.nacl.atomic.rmw.i32(i32, i32*, i32, i32) +declare i64 @llvm.nacl.atomic.rmw.i64(i32, i64*, i64, i32) + + +; TD: declare i8* @llvm.stacksave() +; TD: declare void @llvm.stackrestore(i8*) + +; TD: declare i8* @llvm.nacl.read.tp() +; TD: declare void @llvm.nacl.longjmp(i8*, i32) +; TD: declare void @llvm.nacl.setjmp(i8*) + +; TD: declare void @llvm.memcpy.p0i8.p0i8.i32(i8* nocapture, i8* nocapture, i32, i32, i1) +; TD: declare void @llvm.memmove.p0i8.p0i8.i32(i8* nocapture, i8* nocapture, i32, i32, i1) +; TD: declare void @llvm.memset.p0i8.i32(i8* nocapture, i8, i32, i32, i1) + +; TD: declare i32 @llvm.nacl.atomic.load.i32(i32*, i32) +; TD: declare i64 @llvm.nacl.atomic.load.i64(i64*, i32) + +; TD: declare i32 @llvm.nacl.atomic.cmpxchg.i32(i32*, i32, i32, i32, i32) +; TD: declare i64 @llvm.nacl.atomic.cmpxchg.i64(i64*, i64, i64, i32, i32) + +; TD: declare void @llvm.nacl.atomic.store.i32(i32, i32*, i32) +; TD: declare void @llvm.nacl.atomic.store.i64(i64, i64*, i32) + +; TD: declare i32 @llvm.nacl.atomic.rmw.i32(i32, i32*, i32, i32) +; TD: declare i64 @llvm.nacl.atomic.rmw.i64(i32, i64*, i64, i32) |