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-rw-r--r--test/MC/Mips/do_switch.ll39
-rw-r--r--test/MC/Mips/elf-N64.ll2
-rw-r--r--test/MC/Mips/higher_highest.ll7
-rw-r--r--test/MC/Mips/mips-alu-instructions.s100
-rw-r--r--test/MC/Mips/mips-fpu-instructions.s162
-rw-r--r--test/MC/Mips/mips-jump-instructions.s72
-rw-r--r--test/MC/Mips/mips-memory-instructions.s45
-rw-r--r--test/MC/Mips/mips64extins.ll57
-rw-r--r--test/MC/Mips/mips64shift.ll5
-rw-r--r--test/MC/Mips/mips_directives.s10
-rw-r--r--test/MC/Mips/multi-64bit-func.ll4
11 files changed, 497 insertions, 6 deletions
diff --git a/test/MC/Mips/do_switch.ll b/test/MC/Mips/do_switch.ll
new file mode 100644
index 0000000000..7eda1b41d1
--- /dev/null
+++ b/test/MC/Mips/do_switch.ll
@@ -0,0 +1,39 @@
+; This test case will cause an internal EK_GPRel64BlockAddress to be
+; produced. This was not handled for direct object and an assertion
+; to occur. This is a variation on test case test/CodeGen/Mips/do_switch.ll
+
+; RUN: llc < %s -filetype=obj -march=mips -relocation-model=static
+
+; RUN: llc < %s -filetype=obj -march=mips -relocation-model=pic
+
+; RUN: llc < %s -filetype=obj -march=mips64 -relocation-model=pic -mcpu=mips64 -mattr=n64
+
+define i32 @main() nounwind readnone {
+entry:
+ %x = alloca i32, align 4 ; <i32*> [#uses=2]
+ store volatile i32 2, i32* %x, align 4
+ %0 = load volatile i32* %x, align 4 ; <i32> [#uses=1]
+
+ switch i32 %0, label %bb4 [
+ i32 0, label %bb5
+ i32 1, label %bb1
+ i32 2, label %bb2
+ i32 3, label %bb3
+ ]
+
+bb1: ; preds = %entry
+ ret i32 2
+
+bb2: ; preds = %entry
+ ret i32 0
+
+bb3: ; preds = %entry
+ ret i32 3
+
+bb4: ; preds = %entry
+ ret i32 4
+
+bb5: ; preds = %entry
+ ret i32 1
+}
+
diff --git a/test/MC/Mips/elf-N64.ll b/test/MC/Mips/elf-N64.ll
index 23ec53a2e2..ae6de78d65 100644
--- a/test/MC/Mips/elf-N64.ll
+++ b/test/MC/Mips/elf-N64.ll
@@ -1,4 +1,4 @@
-; RUN: llc -filetype=obj -march=mips64el -mcpu=mips64 %s -o - | elf-dump --dump-section-data | FileCheck %s
+; RUN: llc -filetype=obj -march=mips64el -mcpu=mips64 -disable-mips-delay-filler %s -o - | elf-dump --dump-section-data | FileCheck %s
; Check for N64 relocation production.
;
diff --git a/test/MC/Mips/higher_highest.ll b/test/MC/Mips/higher_highest.ll
index 81a89e3040..0c66522033 100644
--- a/test/MC/Mips/higher_highest.ll
+++ b/test/MC/Mips/higher_highest.ll
@@ -1,5 +1,8 @@
-; RUN: llc -march=mips64el -mcpu=mips64 -mattr=n64 -force-mips-long-branch -filetype=obj < %s -o - | elf-dump --dump-section-data | FileCheck %s
-
+; DISABLE: llc -march=mips64el -mcpu=mips64 -mattr=n64 -force-mips-long-branch -filetype=obj < %s -o - | elf-dump --dump-section-data | FileCheck %s
+; RUN: false
+; XFAIL: *
+; Disabled because currently we don't have a way to generate these relocations.
+;
; Check that the R_MIPS_HIGHER and R_MIPS_HIGHEST relocations were created.
; CHECK: ('r_type', 0x1d)
diff --git a/test/MC/Mips/mips-alu-instructions.s b/test/MC/Mips/mips-alu-instructions.s
new file mode 100644
index 0000000000..2997782cd0
--- /dev/null
+++ b/test/MC/Mips/mips-alu-instructions.s
@@ -0,0 +1,100 @@
+# RUN: llvm-mc %s -triple=mipsel-unknown-linux -show-encoding -mcpu=mips32r2 | FileCheck %s
+# Check that the assembler can handle the documented syntax
+# for arithmetic and logical instructions.
+# CHECK: .section __TEXT,__text,regular,pure_instructions
+#------------------------------------------------------------------------------
+# Logical instructions
+#------------------------------------------------------------------------------
+# CHECK: and $9, $6, $7 # encoding: [0x24,0x48,0xc7,0x00]
+# CHECK: andi $9, $6, 17767 # encoding: [0x67,0x45,0xc9,0x30]
+# CHECK: andi $9, $6, 17767 # encoding: [0x67,0x45,0xc9,0x30]
+# CHECK: clo $6, $7 # encoding: [0x21,0x30,0xe6,0x70]
+# CHECK: clz $6, $7 # encoding: [0x20,0x30,0xe6,0x70]
+# CHECK: ins $19, $9, 6, 7 # encoding: [0x84,0x61,0x33,0x7d]
+# CHECK: nor $9, $6, $7 # encoding: [0x27,0x48,0xc7,0x00]
+# CHECK: or $3, $3, $5 # encoding: [0x25,0x18,0x65,0x00]
+# CHECK: ori $9, $6, 17767 # encoding: [0x67,0x45,0xc9,0x34]
+# CHECK: rotr $9, $6, 7 # encoding: [0xc2,0x49,0x26,0x00]
+# CHECK: rotrv $9, $6, $7 # encoding: [0x46,0x48,0xe6,0x00]
+# CHECK: sll $4, $3, 7 # encoding: [0xc0,0x21,0x03,0x00]
+# CHECK: sllv $2, $3, $5 # encoding: [0x04,0x10,0xa3,0x00]
+# CHECK: slt $3, $3, $5 # encoding: [0x2a,0x18,0x65,0x00]
+# CHECK: slti $3, $3, 103 # encoding: [0x67,0x00,0x63,0x28]
+# CHECK: slti $3, $3, 103 # encoding: [0x67,0x00,0x63,0x28]
+# CHECK: sltiu $3, $3, 103 # encoding: [0x67,0x00,0x63,0x2c]
+# CHECK: sltu $3, $3, $5 # encoding: [0x2b,0x18,0x65,0x00]
+# CHECK: sra $4, $3, 7 # encoding: [0xc3,0x21,0x03,0x00]
+# CHECK: srav $2, $3, $5 # encoding: [0x07,0x10,0xa3,0x00]
+# CHECK: srl $4, $3, 7 # encoding: [0xc2,0x21,0x03,0x00]
+# CHECK: srlv $2, $3, $5 # encoding: [0x06,0x10,0xa3,0x00]
+# CHECK: xor $3, $3, $5 # encoding: [0x26,0x18,0x65,0x00]
+# CHECK: xori $9, $6, 17767 # encoding: [0x67,0x45,0xc9,0x38]
+# CHECK: xori $9, $6, 17767 # encoding: [0x67,0x45,0xc9,0x38]
+# CHECK: wsbh $6, $7 # encoding: [0xa0,0x30,0x07,0x7c]
+# CHECK: nor $7, $8, $zero # encoding: [0x27,0x38,0x00,0x01]
+ and $9, $6, $7
+ and $9, $6, 17767
+ andi $9, $6, 17767
+ clo $6, $7
+ clz $6, $7
+ ins $19, $9, 6,7
+ nor $9, $6, $7
+ or $3, $3, $5
+ ori $9, $6, 17767
+ rotr $9, $6, 7
+ rotrv $9, $6, $7
+ sll $4, $3, 7
+ sllv $2, $3, $5
+ slt $3, $3, $5
+ slt $3, $3, 103
+ slti $3, $3, 103
+ sltiu $3, $3, 103
+ sltu $3, $3, $5
+ sra $4, $3, 7
+ srav $2, $3, $5
+ srl $4, $3, 7
+ srlv $2, $3, $5
+ xor $3, $3, $5
+ xor $9, $6, 17767
+ xori $9, $6, 17767
+ wsbh $6, $7
+ not $7 ,$8
+
+#------------------------------------------------------------------------------
+# Arithmetic instructions
+#------------------------------------------------------------------------------
+
+# CHECK: add $9, $6, $7 # encoding: [0x20,0x48,0xc7,0x00]
+# CHECK: addi $9, $6, 17767 # encoding: [0x67,0x45,0xc9,0x20]
+# CHECK: addiu $9, $6, -15001 # encoding: [0x67,0xc5,0xc9,0x24]
+# CHECK: addi $9, $6, 17767 # encoding: [0x67,0x45,0xc9,0x20]
+# CHECK: addiu $9, $6, -15001 # encoding: [0x67,0xc5,0xc9,0x24]
+# CHECK: addu $9, $6, $7 # encoding: [0x21,0x48,0xc7,0x00]
+# CHECK: madd $6, $7 # encoding: [0x00,0x00,0xc7,0x70]
+# CHECK: maddu $6, $7 # encoding: [0x01,0x00,0xc7,0x70]
+# CHECK: msub $6, $7 # encoding: [0x04,0x00,0xc7,0x70]
+# CHECK: msubu $6, $7 # encoding: [0x05,0x00,0xc7,0x70]
+# CHECK: mult $3, $5 # encoding: [0x18,0x00,0x65,0x00]
+# CHECK: multu $3, $5 # encoding: [0x19,0x00,0x65,0x00]
+# CHECK: sub $9, $6, $7 # encoding: [0x22,0x48,0xc7,0x00]
+# CHECK: subu $4, $3, $5 # encoding: [0x23,0x20,0x65,0x00]
+# CHECK: sub $6, $zero, $7 # encoding: [0x22,0x30,0x07,0x00]
+# CHECK: subu $6, $zero, $7 # encoding: [0x23,0x30,0x07,0x00]
+# CHECK: add $7, $8, $zero # encoding: [0x20,0x38,0x00,0x01]
+ add $9,$6,$7
+ add $9,$6,17767
+ addu $9,$6,-15001
+ addi $9,$6,17767
+ addiu $9,$6,-15001
+ addu $9,$6,$7
+ madd $6,$7
+ maddu $6,$7
+ msub $6,$7
+ msubu $6,$7
+ mult $3,$5
+ multu $3,$5
+ sub $9,$6,$7
+ subu $4,$3,$5
+ neg $6,$7
+ negu $6,$7
+ move $7,$8
diff --git a/test/MC/Mips/mips-fpu-instructions.s b/test/MC/Mips/mips-fpu-instructions.s
new file mode 100644
index 0000000000..ce8024d45b
--- /dev/null
+++ b/test/MC/Mips/mips-fpu-instructions.s
@@ -0,0 +1,162 @@
+# RUN: llvm-mc %s -triple=mipsel-unknown-linux -show-encoding -mcpu=mips32r2 | FileCheck %s
+# Check that the assembler can handle the documented syntax
+# for FPU instructions.
+# CHECK: .section __TEXT,__text,regular,pure_instructions
+#------------------------------------------------------------------------------
+# FP aritmetic instructions
+#------------------------------------------------------------------------------
+
+# CHECK: abs.d $f12, $f14 # encoding: [0x05,0x73,0x20,0x46]
+# CHECK: abs.s $f6, $f7 # encoding: [0x85,0x39,0x00,0x46]
+# CHECK: add.d $f8, $f12, $f14 # encoding: [0x00,0x62,0x2e,0x46]
+# CHECK: add.s $f9, $f6, $f7 # encoding: [0x40,0x32,0x07,0x46]
+# CHECK: floor.w.d $f12, $f14 # encoding: [0x0f,0x73,0x20,0x46]
+# CHECK: floor.w.s $f6, $f7 # encoding: [0x8f,0x39,0x00,0x46]
+# CHECK: ceil.w.d $f12, $f14 # encoding: [0x0e,0x73,0x20,0x46]
+# CHECK: ceil.w.s $f6, $f7 # encoding: [0x8e,0x39,0x00,0x46]
+# CHECK: mul.d $f8, $f12, $f14 # encoding: [0x02,0x62,0x2e,0x46]
+# CHECK: mul.s $f9, $f6, $f7 # encoding: [0x42,0x32,0x07,0x46]
+# CHECK: neg.d $f12, $f14 # encoding: [0x07,0x73,0x20,0x46]
+# CHECK: neg.s $f6, $f7 # encoding: [0x87,0x39,0x00,0x46]
+# CHECK: round.w.d $f12, $f14 # encoding: [0x0c,0x73,0x20,0x46]
+# CHECK: round.w.s $f6, $f7 # encoding: [0x8c,0x39,0x00,0x46]
+# CHECK: sqrt.d $f12, $f14 # encoding: [0x04,0x73,0x20,0x46]
+# CHECK: sqrt.s $f6, $f7 # encoding: [0x84,0x39,0x00,0x46]
+# CHECK: sub.d $f8, $f12, $f14 # encoding: [0x01,0x62,0x2e,0x46]
+# CHECK: sub.s $f9, $f6, $f7 # encoding: [0x41,0x32,0x07,0x46]
+# CHECK: trunc.w.d $f12, $f14 # encoding: [0x0d,0x73,0x20,0x46]
+# CHECK: trunc.w.s $f6, $f7 # encoding: [0x8d,0x39,0x00,0x46]
+
+ abs.d $f12,$f14
+ abs.s $f6,$f7
+ add.d $f8,$f12,$f14
+ add.s $f9,$f6,$f7
+ floor.w.d $f12,$f14
+ floor.w.s $f6,$f7
+ ceil.w.d $f12,$f14
+ ceil.w.s $f6,$f7
+ mul.d $f8,$f12,$f14
+ mul.s $f9,$f6, $f7
+ neg.d $f12,$f14
+ neg.s $f6,$f7
+ round.w.d $f12,$f14
+ round.w.s $f6,$f7
+ sqrt.d $f12,$f14
+ sqrt.s $f6,$f7
+ sub.d $f8,$f12,$f14
+ sub.s $f9,$f6,$f7
+ trunc.w.d $f12,$f14
+ trunc.w.s $f6,$f7
+
+#------------------------------------------------------------------------------
+# FP compare instructions
+#------------------------------------------------------------------------------
+
+# CHECK: c.eq.d $f12, $f14 # encoding: [0x32,0x60,0x2e,0x46]
+# CHECK: c.eq.s $f6, $f7 # encoding: [0x32,0x30,0x07,0x46]
+# CHECK: c.f.d $f12, $f14 # encoding: [0x30,0x60,0x2e,0x46]
+# CHECK: c.f.s $f6, $f7 # encoding: [0x30,0x30,0x07,0x46]
+# CHECK: c.le.d $f12, $f14 # encoding: [0x3e,0x60,0x2e,0x46]
+# CHECK: c.le.s $f6, $f7 # encoding: [0x3e,0x30,0x07,0x46]
+# CHECK: c.lt.d $f12, $f14 # encoding: [0x3c,0x60,0x2e,0x46]
+# CHECK: c.lt.s $f6, $f7 # encoding: [0x3c,0x30,0x07,0x46]
+# CHECK: c.nge.d $f12, $f14 # encoding: [0x3d,0x60,0x2e,0x46]
+# CHECK: c.nge.s $f6, $f7 # encoding: [0x3d,0x30,0x07,0x46]
+# CHECK: c.ngl.d $f12, $f14 # encoding: [0x3b,0x60,0x2e,0x46]
+# CHECK: c.ngl.s $f6, $f7 # encoding: [0x3b,0x30,0x07,0x46]
+# CHECK: c.ngle.d $f12, $f14 # encoding: [0x39,0x60,0x2e,0x46]
+# CHECK: c.ngle.s $f6, $f7 # encoding: [0x39,0x30,0x07,0x46]
+# CHECK: c.ngt.d $f12, $f14 # encoding: [0x3f,0x60,0x2e,0x46]
+# CHECK: c.ngt.s $f6, $f7 # encoding: [0x3f,0x30,0x07,0x46]
+# CHECK: c.ole.d $f12, $f14 # encoding: [0x36,0x60,0x2e,0x46]
+# CHECK: c.ole.s $f6, $f7 # encoding: [0x36,0x30,0x07,0x46]
+# CHECK: c.olt.d $f12, $f14 # encoding: [0x34,0x60,0x2e,0x46]
+# CHECK: c.olt.s $f6, $f7 # encoding: [0x34,0x30,0x07,0x46]
+# CHECK: c.seq.d $f12, $f14 # encoding: [0x3a,0x60,0x2e,0x46]
+# CHECK: c.seq.s $f6, $f7 # encoding: [0x3a,0x30,0x07,0x46]
+# CHECK: c.sf.d $f12, $f14 # encoding: [0x38,0x60,0x2e,0x46]
+# CHECK: c.sf.s $f6, $f7 # encoding: [0x38,0x30,0x07,0x46]
+# CHECK: c.ueq.d $f12, $f14 # encoding: [0x33,0x60,0x2e,0x46]
+# CHECK: c.ueq.s $f28, $f18 # encoding: [0x33,0xe0,0x12,0x46]
+# CHECK: c.ule.d $f12, $f14 # encoding: [0x37,0x60,0x2e,0x46]
+# CHECK: c.ule.s $f6, $f7 # encoding: [0x37,0x30,0x07,0x46]
+# CHECK: c.ult.d $f12, $f14 # encoding: [0x35,0x60,0x2e,0x46]
+# CHECK: c.ult.s $f6, $f7 # encoding: [0x35,0x30,0x07,0x46]
+# CHECK: c.un.d $f12, $f14 # encoding: [0x31,0x60,0x2e,0x46]
+# CHECK: c.un.s $f6, $f7 # encoding: [0x31,0x30,0x07,0x46]
+
+ c.eq.d $f12,$f14
+ c.eq.s $f6,$f7
+ c.f.d $f12,$f14
+ c.f.s $f6,$f7
+ c.le.d $f12,$f14
+ c.le.s $f6,$f7
+ c.lt.d $f12,$f14
+ c.lt.s $f6,$f7
+ c.nge.d $f12,$f14
+ c.nge.s $f6,$f7
+ c.ngl.d $f12,$f14
+ c.ngl.s $f6,$f7
+ c.ngle.d $f12,$f14
+ c.ngle.s $f6,$f7
+ c.ngt.d $f12,$f14
+ c.ngt.s $f6,$f7
+ c.ole.d $f12,$f14
+ c.ole.s $f6,$f7
+ c.olt.d $f12,$f14
+ c.olt.s $f6,$f7
+ c.seq.d $f12,$f14
+ c.seq.s $f6,$f7
+ c.sf.d $f12,$f14
+ c.sf.s $f6,$f7
+ c.ueq.d $f12,$f14
+ c.ueq.s $f28,$f18
+ c.ule.d $f12,$f14
+ c.ule.s $f6,$f7
+ c.ult.d $f12,$f14
+ c.ult.s $f6,$f7
+ c.un.d $f12,$f14
+ c.un.s $f6,$f7
+
+#------------------------------------------------------------------------------
+# FP convert instructions
+#------------------------------------------------------------------------------
+# CHECK: cvt.d.s $f6, $f7 # encoding: [0xa1,0x39,0x00,0x46]
+# CHECK: cvt.d.w $f12, $f14 # encoding: [0x21,0x73,0x80,0x46]
+# CHECK: cvt.s.d $f12, $f14 # encoding: [0x20,0x73,0x20,0x46]
+# CHECK: cvt.s.w $f6, $f7 # encoding: [0xa0,0x39,0x80,0x46]
+# CHECK: cvt.w.d $f12, $f14 # encoding: [0x24,0x73,0x20,0x46]
+# CHECK: cvt.w.s $f6, $f7 # encoding: [0xa4,0x39,0x00,0x46]
+
+ cvt.d.s $f6,$f7
+ cvt.d.w $f12,$f14
+ cvt.s.d $f12,$f14
+ cvt.s.w $f6,$f7
+ cvt.w.d $f12,$f14
+ cvt.w.s $f6,$f7
+
+#------------------------------------------------------------------------------
+# FP move instructions
+#------------------------------------------------------------------------------
+
+# CHECK: cfc1 $6, $fcc0 # encoding: [0x00,0x00,0x46,0x44]
+# CHECK: mfc1 $6, $f7 # encoding: [0x00,0x38,0x06,0x44]
+# CHECK: mfhi $5 # encoding: [0x10,0x28,0x00,0x00]
+# CHECK: mflo $5 # encoding: [0x12,0x28,0x00,0x00]
+# CHECK: mov.d $f6, $f8 # encoding: [0x86,0x41,0x20,0x46]
+# CHECK: mov.s $f6, $f7 # encoding: [0x86,0x39,0x00,0x46]
+# CHECK: mtc1 $6, $f7 # encoding: [0x00,0x38,0x86,0x44]
+# CHECK: mthi $7 # encoding: [0x11,0x00,0xe0,0x00]
+# CHECK: mtlo $7 # encoding: [0x13,0x00,0xe0,0x00]
+# CHECK: swc1 $f9, 9158($7) # encoding: [0xc6,0x23,0xe9,0xe4]
+
+ cfc1 $a2,$0
+ mfc1 $a2,$f7
+ mfhi $a1
+ mflo $a1
+ mov.d $f6,$f8
+ mov.s $f6,$f7
+ mtc1 $a2,$f7
+ mthi $a3
+ mtlo $a3
+ swc1 $f9,9158($a3)
diff --git a/test/MC/Mips/mips-jump-instructions.s b/test/MC/Mips/mips-jump-instructions.s
new file mode 100644
index 0000000000..998be418d2
--- /dev/null
+++ b/test/MC/Mips/mips-jump-instructions.s
@@ -0,0 +1,72 @@
+# RUN: llvm-mc %s -triple=mipsel-unknown-linux -show-encoding -mcpu=mips32r2 | FileCheck %s
+# Check that the assembler can handle the documented syntax
+# for jumps and branches.
+# CHECK: .section __TEXT,__text,regular,pure_instructions
+#------------------------------------------------------------------------------
+# Branch instructions
+#------------------------------------------------------------------------------
+# CHECK: b 1332 # encoding: [0x34,0x05,0x00,0x10]
+# CHECK: nop # encoding: [0x00,0x00,0x00,0x00]
+# CHECK: bc1f 1332 # encoding: [0x34,0x05,0x00,0x45]
+# CHECK: nop # encoding: [0x00,0x00,0x00,0x00]
+# CHECK: bc1t 1332 # encoding: [0x34,0x05,0x01,0x45]
+# CHECK: nop # encoding: [0x00,0x00,0x00,0x00]
+# CHECK: beq $9, $6, 1332 # encoding: [0x34,0x05,0x26,0x11]
+# CHECK: nop # encoding: [0x00,0x00,0x00,0x00]
+# CHECK: bgez $6, 1332 # encoding: [0x34,0x05,0xc1,0x04]
+# CHECK: nop # encoding: [0x00,0x00,0x00,0x00]
+# CHECK: bgezal $6, 1332 # encoding: [0x34,0x05,0xd1,0x04]
+# CHECK: nop # encoding: [0x00,0x00,0x00,0x00]
+# CHECK: bgtz $6, 1332 # encoding: [0x34,0x05,0xc0,0x1c]
+# CHECK: nop # encoding: [0x00,0x00,0x00,0x00]
+# CHECK: blez $6, 1332 # encoding: [0x34,0x05,0xc0,0x18]
+# CHECK: nop # encoding: [0x00,0x00,0x00,0x00]
+# CHECK: bne $9, $6, 1332 # encoding: [0x34,0x05,0x26,0x15]
+# CHECK: nop # encoding: [0x00,0x00,0x00,0x00]
+# CHECK: bal 1332 # encoding: [0x34,0x05,0x00,0x04]
+# CHECK: nop # encoding: [0x00,0x00,0x00,0x00]
+ b 1332
+ nop
+ bc1f 1332
+ nop
+ bc1t 1332
+ nop
+ beq $9,$6,1332
+ nop
+ bgez $6,1332
+ nop
+ bgezal $6,1332
+ nop
+ bgtz $6,1332
+ nop
+ blez $6,1332
+ nop
+ bne $9,$6,1332
+ nop
+ bal 1332
+ nop
+
+end_of_code:
+#------------------------------------------------------------------------------
+# Jump instructions
+#------------------------------------------------------------------------------
+# CHECK: j 1328 # encoding: [0x30,0x05,0x00,0x08]
+# CHECK: nop # encoding: [0x00,0x00,0x00,0x00]
+# CHECK: jal 1328 # encoding: [0x30,0x05,0x00,0x0c]
+# CHECK: nop # encoding: [0x00,0x00,0x00,0x00]
+# CHECK: jalr $6 # encoding: [0x09,0xf8,0xc0,0x00]
+# CHECK: nop # encoding: [0x00,0x00,0x00,0x00]
+# CHECK: jr $7 # encoding: [0x08,0x00,0xe0,0x00]
+# CHECK: nop # encoding: [0x00,0x00,0x00,0x00]
+# CHECK: jr $7 # encoding: [0x08,0x00,0xe0,0x00]
+
+
+ j 1328
+ nop
+ jal 1328
+ nop
+ jalr $6
+ nop
+ jr $7
+ nop
+ j $7
diff --git a/test/MC/Mips/mips-memory-instructions.s b/test/MC/Mips/mips-memory-instructions.s
new file mode 100644
index 0000000000..b5f1267ef3
--- /dev/null
+++ b/test/MC/Mips/mips-memory-instructions.s
@@ -0,0 +1,45 @@
+# RUN: llvm-mc %s -triple=mipsel-unknown-linux -show-encoding -mcpu=mips32r2 | FileCheck %s
+# Check that the assembler can handle the documented syntax
+# for loads and stores.
+# CHECK: .section __TEXT,__text,regular,pure_instructions
+#------------------------------------------------------------------------------
+# Memory store instructions
+#------------------------------------------------------------------------------
+# CHECK: sb $4, 16($5) # encoding: [0x10,0x00,0xa4,0xa0]
+# CHECK: sc $4, 16($5) # encoding: [0x10,0x00,0xa4,0xe0]
+# CHECK: sh $4, 16($5) # encoding: [0x10,0x00,0xa4,0xa4]
+# CHECK: sw $4, 16($5) # encoding: [0x10,0x00,0xa4,0xac]
+# CHECK: sw $7, 0($5) # encoding: [0x00,0x00,0xa7,0xac]
+# CHECK: swc1 $f2, 16($5) # encoding: [0x10,0x00,0xa2,0xe4]
+# CHECK: swl $4, 16($5) # encoding: [0x10,0x00,0xa4,0xa8]
+ sb $4, 16($5)
+ sc $4, 16($5)
+ sh $4, 16($5)
+ sw $4, 16($5)
+ sw $7, ($5)
+ swc1 $f2, 16($5)
+ swl $4, 16($5)
+
+#------------------------------------------------------------------------------
+# Memory load instructions
+#------------------------------------------------------------------------------
+
+# CHECK: lb $4, 4($5) # encoding: [0x04,0x00,0xa4,0x80]
+# CHECK: lw $4, 4($5) # encoding: [0x04,0x00,0xa4,0x8c]
+# CHECK: lbu $4, 4($5) # encoding: [0x04,0x00,0xa4,0x90]
+# CHECK: lh $4, 4($5) # encoding: [0x04,0x00,0xa4,0x84]
+# CHECK: lhu $4, 4($5) # encoding: [0x04,0x00,0xa4,0x94]
+# CHECK: ll $4, 4($5) # encoding: [0x04,0x00,0xa4,0xc0]
+# CHECK: lw $4, 4($5) # encoding: [0x04,0x00,0xa4,0x8c]
+# CHECK: lw $7, 0($7) # encoding: [0x00,0x00,0xe7,0x8c]
+# CHECK: lw $2, 16($sp) # encoding: [0x10,0x00,0xa2,0x8f]
+
+ lb $4, 4($5)
+ lw $4, 4($5)
+ lbu $4, 4($5)
+ lh $4, 4($5)
+ lhu $4, 4($5)
+ ll $4, 4($5)
+ lw $4, 4($5)
+ lw $7, ($7)
+ lw $2, 16($sp)
diff --git a/test/MC/Mips/mips64extins.ll b/test/MC/Mips/mips64extins.ll
new file mode 100644
index 0000000000..ebe8f86513
--- /dev/null
+++ b/test/MC/Mips/mips64extins.ll
@@ -0,0 +1,57 @@
+; RUN: llc -march=mips64el -filetype=obj -mcpu=mips64r2 -mattr=n64 %s -o - \
+; RUN: | llvm-objdump -disassemble -triple mips64el -mattr +mips64r2 - \
+; RUN: | FileCheck %s
+
+define i64 @dext(i64 %i) nounwind readnone {
+entry:
+; CHECK: dext ${{[0-9]+}}, ${{[0-9]+}}, 5, 10
+ %shr = lshr i64 %i, 5
+ %and = and i64 %shr, 1023
+ ret i64 %and
+}
+
+define i64 @dextu(i64 %i) nounwind readnone {
+entry:
+; CHECK: dextu ${{[0-9]+}}, ${{[0-9]+}}, 2, 6
+ %shr = lshr i64 %i, 34
+ %and = and i64 %shr, 63
+ ret i64 %and
+}
+
+define i64 @dextm(i64 %i) nounwind readnone {
+entry:
+; CHECK: dextm ${{[0-9]+}}, ${{[0-9]+}}, 5, 2
+ %shr = lshr i64 %i, 5
+ %and = and i64 %shr, 17179869183
+ ret i64 %and
+}
+
+define i64 @dins(i64 %i, i64 %j) nounwind readnone {
+entry:
+; CHECK: dins ${{[0-9]+}}, ${{[0-9]+}}, 8, 10
+ %shl2 = shl i64 %j, 8
+ %and = and i64 %shl2, 261888
+ %and3 = and i64 %i, -261889
+ %or = or i64 %and3, %and
+ ret i64 %or
+}
+
+define i64 @dinsm(i64 %i, i64 %j) nounwind readnone {
+entry:
+; CHECK: dinsm ${{[0-9]+}}, ${{[0-9]+}}, 10, 1
+ %shl4 = shl i64 %j, 10
+ %and = and i64 %shl4, 8796093021184
+ %and5 = and i64 %i, -8796093021185
+ %or = or i64 %and5, %and
+ ret i64 %or
+}
+
+define i64 @dinsu(i64 %i, i64 %j) nounwind readnone {
+entry:
+; CHECK: dinsu ${{[0-9]+}}, ${{[0-9]+}}, 8, 13
+ %shl4 = shl i64 %j, 40
+ %and = and i64 %shl4, 9006099743113216
+ %and5 = and i64 %i, -9006099743113217
+ %or = or i64 %and5, %and
+ ret i64 %or
+}
diff --git a/test/MC/Mips/mips64shift.ll b/test/MC/Mips/mips64shift.ll
index 7817b96fa5..99cac7b591 100644
--- a/test/MC/Mips/mips64shift.ll
+++ b/test/MC/Mips/mips64shift.ll
@@ -1,5 +1,8 @@
-; RUN: llc -march=mips64el -filetype=obj -mcpu=mips64r2 %s -o - | llvm-objdump -disassemble -triple mips64el - | FileCheck %s
+; RUN: llc -march=mips64el -filetype=obj -mcpu=mips64r2 -disable-mips-delay-filler %s -o - \
+; RUN: | llvm-objdump -disassemble -triple mips64el - | FileCheck %s
+; RUN: llc -march=mips64el -filetype=obj -mcpu=mips64r2 %s -o - \
+; RUN: | llvm-objdump -disassemble -triple mips64el - | FileCheck %s
define i64 @f3(i64 %a0) nounwind readnone {
entry:
diff --git a/test/MC/Mips/mips_directives.s b/test/MC/Mips/mips_directives.s
new file mode 100644
index 0000000000..f9d846078b
--- /dev/null
+++ b/test/MC/Mips/mips_directives.s
@@ -0,0 +1,10 @@
+# RUN: llvm-mc -triple mips-unknown-unknown %s
+
+$BB0_2:
+ .frame $sp,0,$ra
+ .mask 0x00000000,0
+ .fmask 0x00000000,0
+ .set noreorder
+ .set nomacro
+$JTI0_0:
+ .gpword ($BB0_2)
diff --git a/test/MC/Mips/multi-64bit-func.ll b/test/MC/Mips/multi-64bit-func.ll
index 6e0d784e07..83577aa162 100644
--- a/test/MC/Mips/multi-64bit-func.ll
+++ b/test/MC/Mips/multi-64bit-func.ll
@@ -1,8 +1,8 @@
; There is no real check here. If the test doesn't
; assert it passes.
-; RUN: llc -march=mips64el -filetype=obj -mcpu=mips64r2 < %s
+; RUN: llc -march=mips64el -filetype=obj -mcpu=mips64r2 -disable-mips-delay-filler < %s
; Run it again without extra nop in delay slot
-; RUN: llc -march=mips64el -filetype=obj -mcpu=mips64r2 -enable-mips-delay-filler < %s
+; RUN: llc -march=mips64el -filetype=obj -mcpu=mips64r2 < %s
define i32 @bosco1(i32 %x) nounwind readnone {
entry:
generated by cgit v1.2.3-18-g5258 (git 2.32.0) at 2024-11-22 08:29:19 +0000