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-rw-r--r--lib/Target/ARM/ARMExpandPseudoInsts.cpp18
-rw-r--r--lib/Target/ARM/ARMNaClRewritePass.cpp6
-rw-r--r--lib/Target/ARM/ARMSubtarget.h1
3 files changed, 19 insertions, 6 deletions
diff --git a/lib/Target/ARM/ARMExpandPseudoInsts.cpp b/lib/Target/ARM/ARMExpandPseudoInsts.cpp
index eb05665579..7538cf9aa3 100644
--- a/lib/Target/ARM/ARMExpandPseudoInsts.cpp
+++ b/lib/Target/ARM/ARMExpandPseudoInsts.cpp
@@ -949,11 +949,19 @@ bool ARMExpandPseudo::ExpandMI(MachineBasicBlock &MBB,
// See native_client/src/untrusted/nacl/aeabi_read_tp.S
// .nexe builds use this version, while irt builds use a call to
// __aeabi_read_tp.
- // ldr r0, [r9, #0]
- AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(),
- TII->get(ARM::LDRi12), ARM::R0)
- .addReg(ARM::R9)
- .addImm(0));
+ if (FlagNaClUseM23ArmAbi) {
+ // mov r0, r9
+ AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(),
+ TII->get(ARM::MOVr), ARM::R0)
+ .addReg(ARM::R9))
+ .addReg(0); // Doesn't use/modify CPSR.
+ } else {
+ // ldr r0, [r9, #0]
+ AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(),
+ TII->get(ARM::LDRi12), ARM::R0)
+ .addReg(ARM::R9)
+ .addImm(0));
+ }
}
// @LOCALMOD-END
MI.eraseFromParent();
diff --git a/lib/Target/ARM/ARMNaClRewritePass.cpp b/lib/Target/ARM/ARMNaClRewritePass.cpp
index 341d52ea1d..bf3d4596d6 100644
--- a/lib/Target/ARM/ARMNaClRewritePass.cpp
+++ b/lib/Target/ARM/ARMNaClRewritePass.cpp
@@ -53,6 +53,10 @@ FlagSfiStack("sfi-stack", cl::desc("enable sandboxing for stack changes"));
cl::opt<bool>
FlagSfiBranch("sfi-branch", cl::desc("enable sandboxing for branches"));
+cl::opt<bool>
+FlagNaClUseM23ArmAbi("nacl-use-m23-arm-abi",
+ cl::desc("use the Chrome M23 ARM ABI"));
+
}
namespace {
@@ -533,7 +537,7 @@ void ARMNaClRewritePass::SandboxMemory(MachineBasicBlock &MBB,
bool IsLoad) {
unsigned Addr = MI.getOperand(AddrIdx).getReg();
- if (Addr == ARM::R9) {
+ if (!FlagNaClUseM23ArmAbi && Addr == ARM::R9) {
// R9-relative loads are no longer sandboxed.
assert(IsLoad && "There should be no r9-relative stores");
} else if (!CPSRLive && TryPredicating(MI, ARMCC::EQ)) {
diff --git a/lib/Target/ARM/ARMSubtarget.h b/lib/Target/ARM/ARMSubtarget.h
index 64081f5be2..47002a90a3 100644
--- a/lib/Target/ARM/ARMSubtarget.h
+++ b/lib/Target/ARM/ARMSubtarget.h
@@ -27,6 +27,7 @@
#include "llvm/Support/CommandLine.h"
namespace llvm {
extern cl::opt<bool> FlagSfiDisableCP;
+ extern cl::opt<bool> FlagNaClUseM23ArmAbi;
}
// @LOCALMOD-END