diff options
Diffstat (limited to 'lib/Target')
89 files changed, 500 insertions, 476 deletions
diff --git a/lib/Target/ARM/ARMBaseRegisterInfo.cpp b/lib/Target/ARM/ARMBaseRegisterInfo.cpp index e1f179e369..67a4b7d493 100644 --- a/lib/Target/ARM/ARMBaseRegisterInfo.cpp +++ b/lib/Target/ARM/ARMBaseRegisterInfo.cpp @@ -15,7 +15,7 @@ #include "ARMAddressingModes.h" #include "ARMBaseInstrInfo.h" #include "ARMBaseRegisterInfo.h" -#include "ARMFrameInfo.h" +#include "ARMFrameLowering.h" #include "ARMInstrInfo.h" #include "ARMMachineFunctionInfo.h" #include "ARMSubtarget.h" @@ -33,7 +33,7 @@ #include "llvm/Support/Debug.h" #include "llvm/Support/ErrorHandling.h" #include "llvm/Support/raw_ostream.h" -#include "llvm/Target/TargetFrameInfo.h" +#include "llvm/Target/TargetFrameLowering.h" #include "llvm/Target/TargetMachine.h" #include "llvm/Target/TargetOptions.h" #include "llvm/ADT/BitVector.h" @@ -86,7 +86,7 @@ ARMBaseRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const { BitVector ARMBaseRegisterInfo:: getReservedRegs(const MachineFunction &MF) const { - const TargetFrameInfo *TFI = MF.getTarget().getFrameInfo(); + const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); // FIXME: avoid re-calculating this everytime. BitVector Reserved(getNumRegs()); @@ -105,7 +105,7 @@ getReservedRegs(const MachineFunction &MF) const { bool ARMBaseRegisterInfo::isReservedReg(const MachineFunction &MF, unsigned Reg) const { - const TargetFrameInfo *TFI = MF.getTarget().getFrameInfo(); + const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); switch (Reg) { default: break; @@ -354,7 +354,7 @@ std::pair<TargetRegisterClass::iterator,TargetRegisterClass::iterator> ARMBaseRegisterInfo::getAllocationOrder(const TargetRegisterClass *RC, unsigned HintType, unsigned HintReg, const MachineFunction &MF) const { - const TargetFrameInfo *TFI = MF.getTarget().getFrameInfo(); + const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); // Alternative register allocation orders when favoring even / odd registers // of register pairs. @@ -575,7 +575,7 @@ bool ARMBaseRegisterInfo:: needsStackRealignment(const MachineFunction &MF) const { const MachineFrameInfo *MFI = MF.getFrameInfo(); const Function *F = MF.getFunction(); - unsigned StackAlign = MF.getTarget().getFrameInfo()->getStackAlignment(); + unsigned StackAlign = MF.getTarget().getFrameLowering()->getStackAlignment(); bool requiresRealignment = ((MFI->getLocalFrameMaxAlign() > StackAlign) || F->hasFnAttr(Attribute::StackAlignment)); @@ -597,7 +597,7 @@ unsigned ARMBaseRegisterInfo::getRARegister() const { unsigned ARMBaseRegisterInfo::getFrameRegister(const MachineFunction &MF) const { - const TargetFrameInfo *TFI = MF.getTarget().getFrameInfo(); + const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); if (TFI->hasFP(MF)) return FramePtr; @@ -852,7 +852,7 @@ emitSPUpdate(bool isARM, void ARMBaseRegisterInfo:: eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const { - const TargetFrameInfo *TFI = MF.getTarget().getFrameInfo(); + const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); if (!TFI->hasReservedCallFrame(MF)) { // If we have alloca, convert as follows: // ADJCALLSTACKDOWN -> sub, sp, sp, amount @@ -864,7 +864,7 @@ eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, // We need to keep the stack aligned properly. To do this, we round the // amount of space needed for the outgoing arguments up to the next // alignment boundary. - unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment(); + unsigned Align = TFI->getStackAlignment(); Amount = (Amount+Align-1)/Align*Align; ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); @@ -984,7 +984,7 @@ needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const { // Note that the incoming offset is based on the SP value at function entry, // so it'll be negative. MachineFunction &MF = *MI->getParent()->getParent(); - const TargetFrameInfo *TFI = MF.getTarget().getFrameInfo(); + const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); MachineFrameInfo *MFI = MF.getFrameInfo(); ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); @@ -1011,7 +1011,7 @@ needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const { // The FP is only available if there is no dynamic realignment. We // don't know for sure yet whether we'll need that, so we guess based // on whether there are any local variables that would trigger it. - unsigned StackAlign = MF.getTarget().getFrameInfo()->getStackAlignment(); + unsigned StackAlign = TFI->getStackAlignment(); if (TFI->hasFP(MF) && !((MFI->getLocalFrameMaxAlign() > StackAlign) && canRealignStack(MF))) { if (isFrameOffsetLegal(MI, FPOffset)) @@ -1155,8 +1155,8 @@ ARMBaseRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, MachineInstr &MI = *II; MachineBasicBlock &MBB = *MI.getParent(); MachineFunction &MF = *MBB.getParent(); - const ARMFrameInfo *TFI = - static_cast<const ARMFrameInfo*>(MF.getTarget().getFrameInfo()); + const ARMFrameLowering *TFI = + static_cast<const ARMFrameLowering*>(MF.getTarget().getFrameLowering()); ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); assert(!AFI->isThumb1OnlyFunction() && "This eliminateFrameIndex does not support Thumb1!"); diff --git a/lib/Target/ARM/ARMExpandPseudoInsts.cpp b/lib/Target/ARM/ARMExpandPseudoInsts.cpp index 2714dd256d..05d7231c22 100644 --- a/lib/Target/ARM/ARMExpandPseudoInsts.cpp +++ b/lib/Target/ARM/ARMExpandPseudoInsts.cpp @@ -24,7 +24,7 @@ #include "llvm/CodeGen/MachineFrameInfo.h" #include "llvm/CodeGen/MachineFunctionPass.h" #include "llvm/CodeGen/MachineInstrBuilder.h" -#include "llvm/Target/TargetFrameInfo.h" +#include "llvm/Target/TargetFrameLowering.h" #include "llvm/Target/TargetRegisterInfo.h" #include "llvm/Support/raw_ostream.h" // FIXME: for debug only. remove! using namespace llvm; @@ -639,7 +639,7 @@ bool ARMExpandPseudo::ExpandMBB(MachineBasicBlock &MBB) { ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); int32_t NumBytes = AFI->getFramePtrSpillOffset(); unsigned FramePtr = RI.getFrameRegister(MF); - assert(MF.getTarget().getFrameInfo()->hasFP(MF) && + assert(MF.getTarget().getFrameLowering()->hasFP(MF) && "base pointer without frame pointer?"); if (AFI->isThumb2Function()) { diff --git a/lib/Target/ARM/ARMFrameInfo.cpp b/lib/Target/ARM/ARMFrameLowering.cpp index cbc06160d3..824538ccd7 100644 --- a/lib/Target/ARM/ARMFrameInfo.cpp +++ b/lib/Target/ARM/ARMFrameLowering.cpp @@ -1,4 +1,4 @@ -//=======- ARMFrameInfo.cpp - ARM Frame Information ------------*- C++ -*-====// +//=======- ARMFrameLowering.cpp - ARM Frame Information --------*- C++ -*-====// // // The LLVM Compiler Infrastructure // @@ -7,11 +7,11 @@ // //===----------------------------------------------------------------------===// // -// This file contains the ARM implementation of TargetFrameInfo class. +// This file contains the ARM implementation of TargetFrameLowering class. // //===----------------------------------------------------------------------===// -#include "ARMFrameInfo.h" +#include "ARMFrameLowering.h" #include "ARMAddressingModes.h" #include "ARMBaseInstrInfo.h" #include "ARMMachineFunctionInfo.h" @@ -28,7 +28,7 @@ using namespace llvm; /// pointer register. This is true if the function has variable sized allocas /// or if frame pointer elimination is disabled. /// -bool ARMFrameInfo::hasFP(const MachineFunction &MF) const { +bool ARMFrameLowering::hasFP(const MachineFunction &MF) const { const TargetRegisterInfo *RegInfo = MF.getTarget().getRegisterInfo(); // Mac OS X requires FP not to be clobbered for backtracing purpose. @@ -48,7 +48,7 @@ bool ARMFrameInfo::hasFP(const MachineFunction &MF) const { // immediately on entry to the current function. This eliminates the need for // add/sub sp brackets around call sites. Returns true if the call frame is // included as part of the stack frame. -bool ARMFrameInfo::hasReservedCallFrame(const MachineFunction &MF) const { +bool ARMFrameLowering::hasReservedCallFrame(const MachineFunction &MF) const { const MachineFrameInfo *FFI = MF.getFrameInfo(); unsigned CFSize = FFI->getMaxCallFrameSize(); // It's not always a good idea to include the call frame as part of the @@ -65,7 +65,7 @@ bool ARMFrameInfo::hasReservedCallFrame(const MachineFunction &MF) const { // call frame pseudos can be simplified. Unlike most targets, having a FP // is not sufficient here since we still may reference some objects via SP // even when FP is available in Thumb2 mode. -bool ARMFrameInfo::canSimplifyCallFramePseudos(const MachineFunction &MF)const { +bool ARMFrameLowering::canSimplifyCallFramePseudos(const MachineFunction &MF)const { return hasReservedCallFrame(MF) || MF.getFrameInfo()->hasVarSizedObjects(); } @@ -115,7 +115,7 @@ emitSPUpdate(bool isARM, Pred, PredReg, TII); } -void ARMFrameInfo::emitPrologue(MachineFunction &MF) const { +void ARMFrameLowering::emitPrologue(MachineFunction &MF) const { MachineBasicBlock &MBB = MF.front(); MachineBasicBlock::iterator MBBI = MBB.begin(); MachineFrameInfo *MFI = MF.getFrameInfo(); @@ -293,7 +293,7 @@ void ARMFrameInfo::emitPrologue(MachineFunction &MF) const { AFI->setShouldRestoreSPFromFP(true); } -void ARMFrameInfo::emitEpilogue(MachineFunction &MF, +void ARMFrameLowering::emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const { MachineBasicBlock::iterator MBBI = prior(MBB.end()); assert(MBBI->getDesc().isReturn() && @@ -418,13 +418,13 @@ void ARMFrameInfo::emitEpilogue(MachineFunction &MF, // FIXME: This can go wrong when references are SP-relative and simple call // frames aren't used. int -ARMFrameInfo::getFrameIndexReference(const MachineFunction &MF, int FI, +ARMFrameLowering::getFrameIndexReference(const MachineFunction &MF, int FI, unsigned &FrameReg) const { return ResolveFrameIndexReference(MF, FI, FrameReg, 0); } int -ARMFrameInfo::ResolveFrameIndexReference(const MachineFunction &MF, +ARMFrameLowering::ResolveFrameIndexReference(const MachineFunction &MF, int FI, unsigned &FrameReg, int SPAdj) const { @@ -499,12 +499,12 @@ ARMFrameInfo::ResolveFrameIndexReference(const MachineFunction &MF, return Offset; } -int ARMFrameInfo::getFrameIndexOffset(const MachineFunction &MF, int FI) const { +int ARMFrameLowering::getFrameIndexOffset(const MachineFunction &MF, int FI) const { unsigned FrameReg; return getFrameIndexReference(MF, FI, FrameReg); } -void ARMFrameInfo::emitPushInst(MachineBasicBlock &MBB, +void ARMFrameLowering::emitPushInst(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const std::vector<CalleeSavedInfo> &CSI, unsigned StmOpc, unsigned StrOpc, bool NoGap, @@ -572,7 +572,7 @@ void ARMFrameInfo::emitPushInst(MachineBasicBlock &MBB, } } -void ARMFrameInfo::emitPopInst(MachineBasicBlock &MBB, +void ARMFrameLowering::emitPopInst(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const std::vector<CalleeSavedInfo> &CSI, unsigned LdmOpc, unsigned LdrOpc, @@ -642,7 +642,7 @@ void ARMFrameInfo::emitPopInst(MachineBasicBlock &MBB, } } -bool ARMFrameInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB, +bool ARMFrameLowering::spillCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const std::vector<CalleeSavedInfo> &CSI, const TargetRegisterInfo *TRI) const { @@ -663,7 +663,7 @@ bool ARMFrameInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB, return true; } -bool ARMFrameInfo::restoreCalleeSavedRegisters(MachineBasicBlock &MBB, +bool ARMFrameLowering::restoreCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const std::vector<CalleeSavedInfo> &CSI, const TargetRegisterInfo *TRI) const { |