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Diffstat (limited to 'lib/Target/XCore/Disassembler/XCoreDisassembler.cpp')
-rw-r--r--lib/Target/XCore/Disassembler/XCoreDisassembler.cpp150
1 files changed, 120 insertions, 30 deletions
diff --git a/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp b/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp
index 094f18ceee..baa9566490 100644
--- a/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp
+++ b/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp
@@ -132,6 +132,11 @@ static DecodeStatus DecodeLR2RInstruction(MCInst &Inst,
uint64_t Address,
const void *Decoder);
+static DecodeStatus Decode3RInstruction(MCInst &Inst,
+ unsigned Insn,
+ uint64_t Address,
+ const void *Decoder);
+
#include "XCoreGenDisassemblerTables.inc"
static DecodeStatus DecodeGRRegsRegisterClass(MCInst &Inst,
@@ -159,11 +164,15 @@ static DecodeStatus DecodeBitpOperand(MCInst &Inst, unsigned Val,
static DecodeStatus
Decode2OpInstruction(unsigned Insn, unsigned &Op1, unsigned &Op2) {
- unsigned Combined = fieldFromInstruction(Insn, 6, 5) +
- fieldFromInstruction(Insn, 5, 1) * 5 - 27;
- if (Combined >= 9)
+ unsigned Combined = fieldFromInstruction(Insn, 6, 5);
+ if (Combined < 27)
return MCDisassembler::Fail;
-
+ if (fieldFromInstruction(Insn, 5, 1)) {
+ if (Combined == 31)
+ return MCDisassembler::Fail;
+ Combined += 5;
+ }
+ Combined -= 27;
unsigned Op1High = Combined % 3;
unsigned Op2High = Combined / 3;
Op1 = (Op1High << 2) | fieldFromInstruction(Insn, 2, 2);
@@ -172,14 +181,77 @@ Decode2OpInstruction(unsigned Insn, unsigned &Op1, unsigned &Op2) {
}
static DecodeStatus
+Decode3OpInstruction(unsigned Insn, unsigned &Op1, unsigned &Op2,
+ unsigned &Op3) {
+ unsigned Combined = fieldFromInstruction(Insn, 6, 5);
+ if (Combined >= 27)
+ return MCDisassembler::Fail;
+
+ unsigned Op1High = Combined % 3;
+ unsigned Op2High = (Combined / 3) % 3;
+ unsigned Op3High = Combined / 9;
+ Op1 = (Op1High << 2) | fieldFromInstruction(Insn, 4, 2);
+ Op2 = (Op2High << 2) | fieldFromInstruction(Insn, 2, 2);
+ Op3 = (Op3High << 2) | fieldFromInstruction(Insn, 0, 2);
+ return MCDisassembler::Success;
+}
+
+static DecodeStatus
+Decode2OpInstructionFail(MCInst &Inst, unsigned Insn, uint64_t Address,
+ const void *Decoder) {
+ // Try and decode as a 3R instruction.
+ unsigned Opcode = fieldFromInstruction(Insn, 11, 5);
+ switch (Opcode) {
+ case 0x2:
+ Inst.setOpcode(XCore::ADD_3r);
+ return Decode3RInstruction(Inst, Insn, Address, Decoder);
+ case 0x3:
+ Inst.setOpcode(XCore::SUB_3r);
+ return Decode3RInstruction(Inst, Insn, Address, Decoder);
+ case 0x4:
+ Inst.setOpcode(XCore::SHL_3r);
+ return Decode3RInstruction(Inst, Insn, Address, Decoder);
+ case 0x5:
+ Inst.setOpcode(XCore::SHR_3r);
+ return Decode3RInstruction(Inst, Insn, Address, Decoder);
+ case 0x6:
+ Inst.setOpcode(XCore::EQ_3r);
+ return Decode3RInstruction(Inst, Insn, Address, Decoder);
+ case 0x7:
+ Inst.setOpcode(XCore::AND_3r);
+ return Decode3RInstruction(Inst, Insn, Address, Decoder);
+ case 0x8:
+ Inst.setOpcode(XCore::OR_3r);
+ return Decode3RInstruction(Inst, Insn, Address, Decoder);
+ case 0x9:
+ Inst.setOpcode(XCore::LDW_3r);
+ return Decode3RInstruction(Inst, Insn, Address, Decoder);
+ case 0x10:
+ Inst.setOpcode(XCore::LD16S_3r);
+ return Decode3RInstruction(Inst, Insn, Address, Decoder);
+ case 0x11:
+ Inst.setOpcode(XCore::LD8U_3r);
+ return Decode3RInstruction(Inst, Insn, Address, Decoder);
+ case 0x18:
+ Inst.setOpcode(XCore::LSS_3r);
+ return Decode3RInstruction(Inst, Insn, Address, Decoder);
+ case 0x19:
+ Inst.setOpcode(XCore::LSU_3r);
+ return Decode3RInstruction(Inst, Insn, Address, Decoder);
+ }
+ return MCDisassembler::Fail;
+}
+
+static DecodeStatus
Decode2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
const void *Decoder) {
unsigned Op1, Op2;
DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2);
- if (S == MCDisassembler::Success) {
- DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
- DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
- }
+ if (S != MCDisassembler::Success)
+ return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
+
+ DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
+ DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
return S;
}
@@ -188,10 +260,11 @@ DecodeR2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
const void *Decoder) {
unsigned Op1, Op2;
DecodeStatus S = Decode2OpInstruction(Insn, Op2, Op1);
- if (S == MCDisassembler::Success) {
- DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
- DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
- }
+ if (S != MCDisassembler::Success)
+ return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
+
+ DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
+ DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
return S;
}
@@ -200,11 +273,12 @@ Decode2RSrcDstInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
const void *Decoder) {
unsigned Op1, Op2;
DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2);
- if (S == MCDisassembler::Success) {
- DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
- DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
- DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
- }
+ if (S != MCDisassembler::Success)
+ return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
+
+ DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
+ DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
+ DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
return S;
}
@@ -213,10 +287,11 @@ DecodeRUSInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
const void *Decoder) {
unsigned Op1, Op2;
DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2);
- if (S == MCDisassembler::Success) {
- DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
- Inst.addOperand(MCOperand::CreateImm(Op2));
- }
+ if (S != MCDisassembler::Success)
+ return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
+
+ DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
+ Inst.addOperand(MCOperand::CreateImm(Op2));
return S;
}
@@ -225,10 +300,11 @@ DecodeRUSBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
const void *Decoder) {
unsigned Op1, Op2;
DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2);
- if (S == MCDisassembler::Success) {
- DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
- DecodeBitpOperand(Inst, Op2, Address, Decoder);
- }
+ if (S != MCDisassembler::Success)
+ return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
+
+ DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
+ DecodeBitpOperand(Inst, Op2, Address, Decoder);
return S;
}
@@ -237,11 +313,12 @@ DecodeRUSSrcDstBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
const void *Decoder) {
unsigned Op1, Op2;
DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2);
- if (S == MCDisassembler::Success) {
- DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
- DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
- DecodeBitpOperand(Inst, Op2, Address, Decoder);
- }
+ if (S != MCDisassembler::Success)
+ return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
+
+ DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
+ DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
+ DecodeBitpOperand(Inst, Op2, Address, Decoder);
return S;
}
@@ -271,6 +348,19 @@ DecodeLR2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
return S;
}
+static DecodeStatus
+Decode3RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
+ const void *Decoder) {
+ unsigned Op1, Op2, Op3;
+ DecodeStatus S = Decode3OpInstruction(Insn, Op1, Op2, Op3);
+ if (S == MCDisassembler::Success) {
+ DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
+ DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
+ DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
+ }
+ return S;
+}
+
MCDisassembler::DecodeStatus
XCoreDisassembler::getInstruction(MCInst &instr,
uint64_t &Size,
generated by cgit v1.2.3-18-g5258 (git 2.32.0) at 2025-04-25 16:47:54 +0000