diff options
Diffstat (limited to 'lib/Target/X86/InstSelectSimple.cpp')
| -rw-r--r-- | lib/Target/X86/InstSelectSimple.cpp | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/lib/Target/X86/InstSelectSimple.cpp b/lib/Target/X86/InstSelectSimple.cpp index ce86e9cd94..7a1f54e606 100644 --- a/lib/Target/X86/InstSelectSimple.cpp +++ b/lib/Target/X86/InstSelectSimple.cpp @@ -1702,7 +1702,7 @@ void ISel::visitIntrinsicCall(Intrinsic::ID ID, CallInst &CI) { // acceptable range for this architecture. // // - if ((CI.getOperand(1)->getType()->getPrimitiveSize()) != 2) { + if ((CI.getOperand(2)->getType()->getPrimitiveSize()) != 2) { std::cerr << "llvm.writeport: Address size is not 16 bits\n"; exit (1); } @@ -1711,18 +1711,18 @@ void ISel::visitIntrinsicCall(Intrinsic::ID ID, CallInst &CI) { // Now, move the I/O port address into the DX register and the value to // write into the AL/AX/EAX register. // - BuildMI(BB, X86::MOV16rr, 1, X86::DX).addReg(getReg(CI.getOperand(1))); - switch (CI.getOperand(2)->getType()->getPrimitiveSize()) { + BuildMI(BB, X86::MOV16rr, 1, X86::DX).addReg(getReg(CI.getOperand(2))); + switch (CI.getOperand(1)->getType()->getPrimitiveSize()) { case 1: - BuildMI(BB, X86::MOV8rr, 1, X86::AL).addReg(getReg(CI.getOperand(2))); + BuildMI(BB, X86::MOV8rr, 1, X86::AL).addReg(getReg(CI.getOperand(1))); BuildMI(BB, X86::OUT8, 0); break; case 2: - BuildMI(BB, X86::MOV16rr, 1, X86::AX).addReg(getReg(CI.getOperand(2))); + BuildMI(BB, X86::MOV16rr, 1, X86::AX).addReg(getReg(CI.getOperand(1))); BuildMI(BB, X86::OUT16, 0); break; case 4: - BuildMI(BB, X86::MOV32rr, 1, X86::EAX).addReg(getReg(CI.getOperand(2))); + BuildMI(BB, X86::MOV32rr, 1, X86::EAX).addReg(getReg(CI.getOperand(1))); BuildMI(BB, X86::OUT32, 0); break; default: |