diff options
Diffstat (limited to 'lib/Target/Sparc')
| -rw-r--r-- | lib/Target/Sparc/README.txt | 7 | ||||
| -rw-r--r-- | lib/Target/Sparc/SparcISelDAGToDAG.cpp | 8 | ||||
| -rw-r--r-- | lib/Target/Sparc/SparcInstrInfo.td | 36 |
3 files changed, 44 insertions, 7 deletions
diff --git a/lib/Target/Sparc/README.txt b/lib/Target/Sparc/README.txt index f767def153..b08a752a61 100644 --- a/lib/Target/Sparc/README.txt +++ b/lib/Target/Sparc/README.txt @@ -1,10 +1,4 @@ -Meta TODO list: -1. Create a new DAG -> DAG instruction selector, by adding patterns to the - instructions. -2. ??? -3. profit! - To-do ----- @@ -12,4 +6,5 @@ To-do address all of the time. * We can fold small constant offsets into the %hi/%lo references to constant pool addresses as well. +* When in V9 mode, register allocate %icc[0-3]. diff --git a/lib/Target/Sparc/SparcISelDAGToDAG.cpp b/lib/Target/Sparc/SparcISelDAGToDAG.cpp index b02e8600b4..9718801a8a 100644 --- a/lib/Target/Sparc/SparcISelDAGToDAG.cpp +++ b/lib/Target/Sparc/SparcISelDAGToDAG.cpp @@ -850,9 +850,15 @@ SparcV8TargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI, namespace { class SparcV8DAGToDAGISel : public SelectionDAGISel { SparcV8TargetLowering V8Lowering; + + /// Subtarget - Keep a pointer to the Sparc Subtarget around so that we can + /// make the right decision when generating code for different targets. + const SparcV8Subtarget &Subtarget; public: SparcV8DAGToDAGISel(TargetMachine &TM) - : SelectionDAGISel(V8Lowering), V8Lowering(TM) {} + : SelectionDAGISel(V8Lowering), V8Lowering(TM), + Subtarget(TM.getSubtarget<SparcV8Subtarget>()) { + } SDOperand Select(SDOperand Op); diff --git a/lib/Target/Sparc/SparcInstrInfo.td b/lib/Target/Sparc/SparcInstrInfo.td index 8269448ca1..44f83e1944 100644 --- a/lib/Target/Sparc/SparcInstrInfo.td +++ b/lib/Target/Sparc/SparcInstrInfo.td @@ -18,6 +18,23 @@ include "SparcV8InstrFormats.td" //===----------------------------------------------------------------------===// +// Feature predicates. +//===----------------------------------------------------------------------===// + +// HasV9 - This predicate is true when the target processor supports V9 +// instructions. Note that the machine may be running in 32-bit mode. +def HasV9 : Predicate<"Subtarget.isV9()">; + +// HasVIS - This is true when the target processor has VIS extensions. +def HasVIS : Predicate<"Subtarget.isVIS()">; + +// UseDeprecatedInsts - This predicate is true when the target processor is a +// V8, or when it is V9 but the V8 deprecated instructions are efficient enough +// to use when appropriate. In either of these cases, the instruction selector +// will pick deprecated instructions. +def UseDeprecatedInsts : Predicate<"Subtarget.useDeprecatedV8Instructions()">; + +//===----------------------------------------------------------------------===// // Instruction Pattern Stuff //===----------------------------------------------------------------------===// @@ -168,6 +185,7 @@ let usesCustomDAGSchedInserter = 1 in { // Expanded by the scheduler. imm:$Cond, FCC))]>; } + // Section A.3 - Synthetic Instructions, p. 85 // special cases of JMPL: let isReturn = 1, isTerminator = 1, hasDelaySlot = 1, noResults = 1 in { @@ -706,6 +724,24 @@ def FCMPD : F3_3<2, 0b110101, 0b001010010, "fcmpd $src1, $src2\n\tnop", [(set FCC, (V8cmpfcc DFPRegs:$src1, DFPRegs:$src2))]>; + +//===----------------------------------------------------------------------===// +// V9 Instructions +//===----------------------------------------------------------------------===// + +// V9 Conditional Moves. +let Predicates = [HasV9], isTwoAddress = 1 in { + // FIXME: Add instruction encodings for the JIT some day. + def MOVNE : Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F), + "movne %icc, $F, $dst", + [(set IntRegs:$dst, + (V8selecticc IntRegs:$F, IntRegs:$T, 22, ICC))]>; + def MOVEQ : Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F), + "move %icc, $F, $dst", + [(set IntRegs:$dst, + (V8selecticc IntRegs:$F, IntRegs:$T, 17, ICC))]>; +} + //===----------------------------------------------------------------------===// // Non-Instruction Patterns //===----------------------------------------------------------------------===// |