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-rw-r--r--lib/Target/PowerPC/PPCInstrInfo.td13
1 files changed, 9 insertions, 4 deletions
diff --git a/lib/Target/PowerPC/PPCInstrInfo.td b/lib/Target/PowerPC/PPCInstrInfo.td
index 02b066f582..81332c1acd 100644
--- a/lib/Target/PowerPC/PPCInstrInfo.td
+++ b/lib/Target/PowerPC/PPCInstrInfo.td
@@ -255,9 +255,11 @@ def memrix : Operand<iPTR> { // memri where the imm is shifted 2 bits.
let MIOperandInfo = (ops i32imm, ptr_rc);
}
-// PowerPC Predicate operand. 20 = always, CR0 is a dummy reg that doesn't
-// matter.
-def pred : PredicateOperand<(ops imm, CRRC), (ops 20, CR0)>;
+// PowerPC Predicate operand. 640 = ((20<<5)|0) = always, CR0 is a dummy reg
+// that doesn't matter.
+def pred : PredicateOperand<(ops imm, CRRC), (ops (i32 640), CR0)> {
+ let PrintMethod = "printPredicateOperand";
+}
// Define PowerPC specific addressing mode.
def iaddr : ComplexPattern<iPTR, 2, "SelectAddrImm", [], []>;
@@ -315,10 +317,13 @@ let usesCustomDAGSchedInserter = 1, // Expanded by the scheduler.
let isTerminator = 1, isBarrier = 1, noResults = 1, PPC970_Unit = 7 in {
let isReturn = 1 in
- def BLR : XLForm_2_ext<19, 16, 20, 0, 0, (ops), "blr", BrB, [(retflag)]>;
+ def BLR : XLForm_2_ext<19, 16, 20, 0, 0,
+ (ops pred:$p),
+ "b${p:cc}lr ${p:reg}", BrB, [(retflag)]>;
def BCTR : XLForm_2_ext<19, 528, 20, 0, 0, (ops), "bctr", BrB, []>;
}
+
let Defs = [LR] in
def MovePCtoLR : Pseudo<(ops piclabel:$label), "bl $label", []>,
PPC970_Unit_BRU;