aboutsummaryrefslogtreecommitdiff
path: root/lib/Target/Mips/MipsInstrFPU.td
diff options
context:
space:
mode:
Diffstat (limited to 'lib/Target/Mips/MipsInstrFPU.td')
-rw-r--r--lib/Target/Mips/MipsInstrFPU.td2
1 files changed, 1 insertions, 1 deletions
diff --git a/lib/Target/Mips/MipsInstrFPU.td b/lib/Target/Mips/MipsInstrFPU.td
index 251f377769..995b6cd071 100644
--- a/lib/Target/Mips/MipsInstrFPU.td
+++ b/lib/Target/Mips/MipsInstrFPU.td
@@ -187,7 +187,7 @@ let Predicates = [IsNotSingleFloat, IsNotMipsI] in {
"sdc1 $ft, $addr", [(store AFGR64:$ft, addr:$addr)]>;
}
-// LWC1 and SWC1 can always be emited with odd registers.
+// LWC1 and SWC1 can always be emitted with odd registers.
def LWC1 : FFI<0b110001, (outs FGR32:$ft), (ins mem:$addr), "lwc1 $ft, $addr",
[(set FGR32:$ft, (load addr:$addr))]>;
def SWC1 : FFI<0b111001, (outs), (ins FGR32:$ft, mem:$addr), "swc1 $ft, $addr",