diff options
Diffstat (limited to 'lib/Target/Mips/Disassembler/MipsDisassembler.cpp')
| -rw-r--r-- | lib/Target/Mips/Disassembler/MipsDisassembler.cpp | 84 |
1 files changed, 17 insertions, 67 deletions
diff --git a/lib/Target/Mips/Disassembler/MipsDisassembler.cpp b/lib/Target/Mips/Disassembler/MipsDisassembler.cpp index 571a48101f..b59997d04a 100644 --- a/lib/Target/Mips/Disassembler/MipsDisassembler.cpp +++ b/lib/Target/Mips/Disassembler/MipsDisassembler.cpp @@ -13,16 +13,15 @@ #include "Mips.h" #include "MipsSubtarget.h" +#include "MipsRegisterInfo.h" #include "llvm/MC/EDInstInfo.h" #include "llvm/MC/MCDisassembler.h" #include "llvm/Support/MemoryObject.h" #include "llvm/Support/TargetRegistry.h" #include "llvm/MC/MCSubtargetInfo.h" #include "llvm/MC/MCInst.h" -#include "llvm/MC/MCRegisterInfo.h" #include "llvm/Support/MathExtras.h" - #include "MipsGenEDInfo.inc" using namespace llvm; @@ -96,58 +95,6 @@ const EDInstInfo *Mips64Disassembler::getEDInfo() const { return instInfoMips; } -// Decoder tables for Mips register -static const uint16_t CPURegsTable[] = { - Mips::ZERO, Mips::AT, Mips::V0, Mips::V1, - Mips::A0, Mips::A1, Mips::A2, Mips::A3, - Mips::T0, Mips::T1, Mips::T2, Mips::T3, - Mips::T4, Mips::T5, Mips::T6, Mips::T7, - Mips::S0, Mips::S1, Mips::S2, Mips::S3, - Mips::S4, Mips::S5, Mips::S6, Mips::S7, - Mips::T8, Mips::T9, Mips::K0, Mips::K1, - Mips::GP, Mips::SP, Mips::FP, Mips::RA -}; - -static const uint16_t FGR32RegsTable[] = { - Mips::F0, Mips::F1, Mips::F2, Mips::F3, - Mips::F4, Mips::F5, Mips::F6, Mips::F7, - Mips::F8, Mips::F9, Mips::F10, Mips::F11, - Mips::F12, Mips::F13, Mips::F14, Mips::F15, - Mips::F16, Mips::F17, Mips::F18, Mips::F18, - Mips::F20, Mips::F21, Mips::F22, Mips::F23, - Mips::F24, Mips::F25, Mips::F26, Mips::F27, - Mips::F28, Mips::F29, Mips::F30, Mips::F31 -}; - -static const uint16_t CPU64RegsTable[] = { - Mips::ZERO_64, Mips::AT_64, Mips::V0_64, Mips::V1_64, - Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64, - Mips::T0_64, Mips::T1_64, Mips::T2_64, Mips::T3_64, - Mips::T4_64, Mips::T5_64, Mips::T6_64, Mips::T7_64, - Mips::S0_64, Mips::S1_64, Mips::S2_64, Mips::S3_64, - Mips::S4_64, Mips::S5_64, Mips::S6_64, Mips::S7_64, - Mips::T8_64, Mips::T9_64, Mips::K0_64, Mips::K1_64, - Mips::GP_64, Mips::SP_64, Mips::FP_64, Mips::RA_64 -}; - -static const uint16_t FGR64RegsTable[] = { - Mips::D0_64, Mips::D1_64, Mips::D2_64, Mips::D3_64, - Mips::D4_64, Mips::D5_64, Mips::D6_64, Mips::D7_64, - Mips::D8_64, Mips::D9_64, Mips::D10_64, Mips::D11_64, - Mips::D12_64, Mips::D13_64, Mips::D14_64, Mips::D15_64, - Mips::D16_64, Mips::D17_64, Mips::D18_64, Mips::D19_64, - Mips::D20_64, Mips::D21_64, Mips::D22_64, Mips::D23_64, - Mips::D24_64, Mips::D25_64, Mips::D26_64, Mips::D27_64, - Mips::D28_64, Mips::D29_64, Mips::D30_64, Mips::D31_64 -}; - -static const uint16_t AFGR64RegsTable[] = { - Mips::D0, Mips::D1, Mips::D2, Mips::D3, - Mips::D4, Mips::D5, Mips::D6, Mips::D7, - Mips::D8, Mips::D9, Mips::D10, Mips::D11, - Mips::D12, Mips::D13, Mips::D14, Mips::D15 -}; - // Forward declare these because the autogenerated code will reference them. // Definitions are further down. static DecodeStatus DecodeCPU64RegsRegisterClass(MCInst &Inst, @@ -366,6 +313,9 @@ Mips64Disassembler::getInstruction(MCInst &instr, return MCDisassembler::Fail; } +#define GET_REGINFO_TARGET_DESC +#include "MipsGenRegisterInfo.inc" + static DecodeStatus DecodeCPU64RegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, @@ -374,7 +324,7 @@ static DecodeStatus DecodeCPU64RegsRegisterClass(MCInst &Inst, if (RegNo > 31) return MCDisassembler::Fail; - Inst.addOperand(MCOperand::CreateReg(CPU64RegsTable[RegNo])); + Inst.addOperand(MCOperand::CreateReg(*(Mips::CPU64RegsRegClass.begin() + RegNo))); return MCDisassembler::Success; } @@ -384,8 +334,7 @@ static DecodeStatus DecodeCPURegsRegisterClass(MCInst &Inst, const void *Decoder) { if (RegNo > 31) return MCDisassembler::Fail; - - Inst.addOperand(MCOperand::CreateReg(CPURegsTable[RegNo])); + Inst.addOperand(MCOperand::CreateReg(*(Mips::CPURegsRegClass.begin() + RegNo))); return MCDisassembler::Success; } @@ -396,7 +345,7 @@ static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst, if (RegNo > 31) return MCDisassembler::Fail; - Inst.addOperand(MCOperand::CreateReg(FGR64RegsTable[RegNo])); + Inst.addOperand(MCOperand::CreateReg(*(Mips::FGR64RegClass.begin() + RegNo))); return MCDisassembler::Success; } @@ -407,7 +356,7 @@ static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst, if (RegNo > 31) return MCDisassembler::Fail; - Inst.addOperand(MCOperand::CreateReg(FGR32RegsTable[RegNo])); + Inst.addOperand(MCOperand::CreateReg(*(Mips::FGR32RegClass.begin() + RegNo))); return MCDisassembler::Success; } @@ -428,11 +377,11 @@ static DecodeStatus DecodeMem(MCInst &Inst, int Base = (int)fieldFromInstruction32(Insn, 21, 5); if(Inst.getOpcode() == Mips::SC){ - Inst.addOperand(MCOperand::CreateReg(CPURegsTable[Reg])); + Inst.addOperand(MCOperand::CreateReg(*(Mips::CPURegsRegClass.begin() + Reg))); } - Inst.addOperand(MCOperand::CreateReg(CPURegsTable[Reg])); - Inst.addOperand(MCOperand::CreateReg(CPURegsTable[Base])); + Inst.addOperand(MCOperand::CreateReg(*(Mips::CPURegsRegClass.begin() + Reg))); + Inst.addOperand(MCOperand::CreateReg(*(Mips::CPURegsRegClass.begin() + Base))); Inst.addOperand(MCOperand::CreateImm(Offset)); return MCDisassembler::Success; @@ -446,8 +395,8 @@ static DecodeStatus DecodeFMem(MCInst &Inst, int Reg = (int)fieldFromInstruction32(Insn, 16, 5); int Base = (int)fieldFromInstruction32(Insn, 21, 5); - Inst.addOperand(MCOperand::CreateReg(FGR64RegsTable[Reg])); - Inst.addOperand(MCOperand::CreateReg(CPURegsTable[Base])); + Inst.addOperand(MCOperand::CreateReg(*(Mips::FGR64RegClass.begin() + Reg))); + Inst.addOperand(MCOperand::CreateReg(*(Mips::CPURegsRegClass.begin() + Base))); Inst.addOperand(MCOperand::CreateImm(Offset)); return MCDisassembler::Success; @@ -478,10 +427,11 @@ static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) { - if (RegNo > 31) + if (RegNo > 30 || RegNo %2) return MCDisassembler::Fail; - Inst.addOperand(MCOperand::CreateReg(AFGR64RegsTable[RegNo])); + RegNo /=2; + Inst.addOperand(MCOperand::CreateReg(*(Mips::AFGR64RegClass.begin() + RegNo))); return MCDisassembler::Success; } @@ -492,7 +442,7 @@ static DecodeStatus DecodeHWRegs64RegisterClass(MCInst &Inst, //Currently only hardware register 29 is supported if (RegNo != 29) return MCDisassembler::Fail; - Inst.addOperand(MCOperand::CreateReg(Mips::HWR29)); + Inst.addOperand(MCOperand::CreateReg(Mips::HWR29_64)); return MCDisassembler::Success; } |