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-rw-r--r--lib/CodeGen/MachineInstr.cpp18
-rw-r--r--lib/CodeGen/RegAllocLinearScan.cpp56
-rw-r--r--lib/CodeGen/TwoAddressInstructionPass.cpp124
3 files changed, 94 insertions, 104 deletions
diff --git a/lib/CodeGen/MachineInstr.cpp b/lib/CodeGen/MachineInstr.cpp
index 869d963d53..9d7b1b2d99 100644
--- a/lib/CodeGen/MachineInstr.cpp
+++ b/lib/CodeGen/MachineInstr.cpp
@@ -27,24 +27,6 @@ namespace llvm {
//
extern const TargetInstrDescriptor *TargetInstrDescriptors;
-bool MachineOperand::isEverUsed(const MachineInstr& mi) const
-{
- for (int i = 0, e = mi.getNumOperands(); i != e; ++i) {
- if (*this == mi.getOperand(i) && mi.getOperand(i).isUse())
- return true;
- }
- return false;
-}
-
-bool MachineOperand::isEverDefined(const MachineInstr& mi) const
-{
- for (int i = 0, e = mi.getNumOperands(); i != e; ++i) {
- if (*this == mi.getOperand(i) && mi.getOperand(i).isDef())
- return true;
- }
- return false;
-}
-
// Constructor for instructions with variable #operands
MachineInstr::MachineInstr(MachineOpCode OpCode, unsigned numOperands)
: opCode(OpCode),
diff --git a/lib/CodeGen/RegAllocLinearScan.cpp b/lib/CodeGen/RegAllocLinearScan.cpp
index b71a138616..7a7c1c0bb9 100644
--- a/lib/CodeGen/RegAllocLinearScan.cpp
+++ b/lib/CodeGen/RegAllocLinearScan.cpp
@@ -109,10 +109,6 @@ namespace {
typedef std::vector<const LiveIntervals::Interval*> IntervalPtrs;
IntervalPtrs unhandled_, fixed_, active_, inactive_;
- typedef std::vector<unsigned> Regs;
- Regs tempUseOperands_;
- Regs tempDefOperands_;
-
PhysRegTracker prt_;
typedef std::map<unsigned, unsigned> Virt2PhysMap;
@@ -428,7 +424,6 @@ bool RA::runOnMachineFunction(MachineFunction &fn) {
for (currentInstr_ = currentMbb_->begin();
currentInstr_ != currentMbb_->end(); ) {
-
DEBUG(std::cerr << "\tinstruction: ";
(*currentInstr_)->print(std::cerr, *tm_););
@@ -465,13 +460,17 @@ bool RA::runOnMachineFunction(MachineFunction &fn) {
continue;
}
+ typedef std::vector<unsigned> Regs;
+ Regs toClear;
+ Regs toSpill;
+
+ const unsigned numOperands = (*currentInstr_)->getNumOperands();
+
DEBUG(std::cerr << "\t\tloading temporarily used operands to "
"registers:\n");
- for (unsigned i = 0, e = (*currentInstr_)->getNumOperands();
- i != e; ++i) {
+ for (unsigned i = 0; i != numOperands; ++i) {
MachineOperand& op = (*currentInstr_)->getOperand(i);
- if (op.isVirtualRegister() && op.isUse() &&
- !op.isEverDefined(**currentInstr_)) {
+ if (op.isVirtualRegister() && op.isUse()) {
unsigned virtReg = op.getAllocatedRegNum();
unsigned physReg = 0;
Virt2PhysMap::const_iterator it = v2pMap_.find(virtReg);
@@ -481,26 +480,28 @@ bool RA::runOnMachineFunction(MachineFunction &fn) {
else {
physReg = getFreeTempPhysReg(virtReg);
loadVirt2PhysReg(virtReg, physReg);
- tempUseOperands_.push_back(virtReg);
+ // we will clear uses that are not also defs
+ // before we allocate registers the defs
+ if (op.isDef())
+ toSpill.push_back(virtReg);
+ else
+ toClear.push_back(virtReg);
}
(*currentInstr_)->SetMachineOperandReg(i, physReg);
}
}
- DEBUG(std::cerr << "\t\tclearing temporarily used operands:\n");
- for (unsigned i = 0, e = tempUseOperands_.size(); i != e; ++i) {
- clearVirtReg(tempUseOperands_[i]);
- }
- tempUseOperands_.clear();
+ DEBUG(std::cerr << "\t\tclearing temporarily used but not defined "
+ "operands:\n");
+ std::for_each(toClear.begin(), toClear.end(),
+ std::bind1st(std::mem_fun(&RA::clearVirtReg), this));
DEBUG(std::cerr << "\t\tassigning temporarily defined operands to "
"registers:\n");
- for (unsigned i = 0, e = (*currentInstr_)->getNumOperands();
- i != e; ++i) {
+ for (unsigned i = 0; i != numOperands; ++i) {
MachineOperand& op = (*currentInstr_)->getOperand(i);
if (op.isVirtualRegister()) {
- assert(op.isEverDefined(**currentInstr_) &&
- "operand should be defined by this instruction");
+ assert(!op.isUse() && "we should not have uses here!");
unsigned virtReg = op.getAllocatedRegNum();
unsigned physReg = 0;
Virt2PhysMap::const_iterator it = v2pMap_.find(virtReg);
@@ -510,21 +511,18 @@ bool RA::runOnMachineFunction(MachineFunction &fn) {
else {
physReg = getFreeTempPhysReg(virtReg);
assignVirt2PhysReg(virtReg, physReg);
- tempDefOperands_.push_back(virtReg);
+ // need to spill this after we are done with
+ // this instruction
+ toSpill.push_back(virtReg);
}
(*currentInstr_)->SetMachineOperandReg(i, physReg);
}
}
+ ++currentInstr_; // spills will go after this instruction
- DEBUG(std::cerr << "\t\tspilling temporarily defined operands "
- "of this instruction:\n");
- ++currentInstr_; // we want to insert after this instruction
- for (unsigned i = 0, e = tempDefOperands_.size(); i != e; ++i) {
- spillVirtReg(tempDefOperands_[i]);
- }
- --currentInstr_; // restore currentInstr_ iterator
- tempDefOperands_.clear();
- ++currentInstr_;
+ DEBUG(std::cerr << "\t\tspilling temporarily defined operands:\n");
+ std::for_each(toSpill.begin(), toSpill.end(),
+ std::bind1st(std::mem_fun(&RA::spillVirtReg), this));
}
}
diff --git a/lib/CodeGen/TwoAddressInstructionPass.cpp b/lib/CodeGen/TwoAddressInstructionPass.cpp
index 991be42e53..dd94d40d8b 100644
--- a/lib/CodeGen/TwoAddressInstructionPass.cpp
+++ b/lib/CodeGen/TwoAddressInstructionPass.cpp
@@ -16,11 +16,14 @@
// to:
//
// A = B
-// A = A op C
+// A op= C
//
-// Note that if a register allocator chooses to use this pass, that it has to
-// be capable of handling the non-SSA nature of these rewritten virtual
-// registers.
+// Note that if a register allocator chooses to use this pass, that it
+// has to be capable of handling the non-SSA nature of these rewritten
+// virtual registers.
+//
+// It is also worth noting that the duplicate operand of the two
+// address instruction is removed.
//
//===----------------------------------------------------------------------===//
@@ -98,63 +101,70 @@ bool TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &MF) {
mi->getOperand(1).isUse() &&
"two address instruction invalid");
- // we have nothing to do if the two operands are the same
+ // if the two operands are the same we just remove the use
+ // and mark the def as def&use
if (mi->getOperand(0).getAllocatedRegNum() ==
- mi->getOperand(1).getAllocatedRegNum())
- continue;
-
- MadeChange = true;
-
- // rewrite:
- // a = b op c
- // to:
- // a = b
- // a = a op c
- unsigned regA = mi->getOperand(0).getAllocatedRegNum();
- unsigned regB = mi->getOperand(1).getAllocatedRegNum();
-
- assert(MRegisterInfo::isVirtualRegister(regA) &&
- MRegisterInfo::isVirtualRegister(regB) &&
- "cannot update physical register live information");
-
- // first make sure we do not have a use of a in the
- // instruction (a = b + a for example) because our
- // transformation will not work. This should never occur
- // because we are in SSA form.
- for (unsigned i = 1; i != mi->getNumOperands(); ++i)
- assert(!mi->getOperand(i).isRegister() ||
- mi->getOperand(i).getAllocatedRegNum() != (int)regA);
-
- const TargetRegisterClass* rc =MF.getSSARegMap()->getRegClass(regA);
- unsigned Added = MRI.copyRegToReg(*mbbi, mii, regA, regB, rc);
- numInstrsAdded += Added;
-
- MachineInstr* prevMi = *(mii - 1);
- DEBUG(std::cerr << "\t\tadded instruction: ";
- prevMi->print(std::cerr, TM));
-
- // update live variables for regA
- assert(Added == 1 && "Cannot handle multi-instruction copies yet!");
- LiveVariables::VarInfo& varInfo = LV.getVarInfo(regA);
- varInfo.DefInst = prevMi;
-
- // update live variables for regB
- if (LV.removeVirtualRegisterKilled(regB, &*mbbi, mi))
- LV.addVirtualRegisterKilled(regB, &*mbbi, prevMi);
-
- if (LV.removeVirtualRegisterDead(regB, &*mbbi, mi))
- LV.addVirtualRegisterDead(regB, &*mbbi, prevMi);
-
- // replace all occurences of regB with regA
- for (unsigned i = 1; i < mi->getNumOperands(); ++i) {
- if (mi->getOperand(i).isRegister() &&
- mi->getOperand(i).getReg() == regB)
- mi->SetMachineOperandReg(i, regA);
+ mi->getOperand(1).getAllocatedRegNum()) {
}
+ else {
+ MadeChange = true;
+
+ // rewrite:
+ // a = b op c
+ // to:
+ // a = b
+ // a = a op c
+ unsigned regA = mi->getOperand(0).getAllocatedRegNum();
+ unsigned regB = mi->getOperand(1).getAllocatedRegNum();
+
+ assert(MRegisterInfo::isVirtualRegister(regA) &&
+ MRegisterInfo::isVirtualRegister(regB) &&
+ "cannot update physical register live information");
+
+ // first make sure we do not have a use of a in the
+ // instruction (a = b + a for example) because our
+ // transformation will not work. This should never occur
+ // because we are in SSA form.
+ for (unsigned i = 1; i != mi->getNumOperands(); ++i)
+ assert(!mi->getOperand(i).isRegister() ||
+ mi->getOperand(i).getAllocatedRegNum() != (int)regA);
+
+ const TargetRegisterClass* rc =
+ MF.getSSARegMap()->getRegClass(regA);
+ unsigned Added = MRI.copyRegToReg(*mbbi, mii, regA, regB, rc);
+ numInstrsAdded += Added;
+
+ MachineInstr* prevMi = *(mii - 1);
+ DEBUG(std::cerr << "\t\tadded instruction: ";
+ prevMi->print(std::cerr, TM));
+
+ // update live variables for regA
+ assert(Added == 1 &&
+ "Cannot handle multi-instruction copies yet!");
+ LiveVariables::VarInfo& varInfo = LV.getVarInfo(regA);
+ varInfo.DefInst = prevMi;
+
+ // update live variables for regB
+ if (LV.removeVirtualRegisterKilled(regB, &*mbbi, mi))
+ LV.addVirtualRegisterKilled(regB, &*mbbi, prevMi);
+
+ if (LV.removeVirtualRegisterDead(regB, &*mbbi, mi))
+ LV.addVirtualRegisterDead(regB, &*mbbi, prevMi);
+
+ // replace all occurences of regB with regA
+ for (unsigned i = 1, e = mi->getNumOperands(); i != e; ++i) {
+ if (mi->getOperand(i).isRegister() &&
+ mi->getOperand(i).getReg() == regB)
+ mi->SetMachineOperandReg(i, regA);
+ }
+ }
+
+ assert(mi->getOperand(0).isDef());
+ mi->getOperand(0).setUse();
+ mi->RemoveOperand(1);
+
DEBUG(std::cerr << "\t\tmodified original to: ";
mi->print(std::cerr, TM));
- assert(mi->getOperand(0).getAllocatedRegNum() ==
- mi->getOperand(1).getAllocatedRegNum());
}
}
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