diff options
Diffstat (limited to 'lib/CodeGen/SelectionDAG/LegalizeDAG.cpp')
| -rw-r--r-- | lib/CodeGen/SelectionDAG/LegalizeDAG.cpp | 572 |
1 files changed, 282 insertions, 290 deletions
diff --git a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp index 99f1a0355d..83ba08da18 100644 --- a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp +++ b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp @@ -128,13 +128,13 @@ public: /// getTypeAction - Return how we should legalize values of this type, either /// it is already legal or we need to expand it into multiple registers of /// smaller integer type, or we need to promote it to a larger type. - LegalizeAction getTypeAction(MVT::ValueType VT) const { + LegalizeAction getTypeAction(MVT VT) const { return (LegalizeAction)ValueTypeActions.getTypeAction(VT); } /// isTypeLegal - Return true if this type is legal on this target. /// - bool isTypeLegal(MVT::ValueType VT) const { + bool isTypeLegal(MVT VT) const { return getTypeAction(VT) == Legal; } @@ -196,7 +196,7 @@ private: /// /// If this is a legal shuffle, this method returns the (possibly promoted) /// build_vector Mask. If it's not a legal shuffle, it returns null. - SDNode *isShuffleLegal(MVT::ValueType VT, SDOperand Mask) const; + SDNode *isShuffleLegal(MVT VT, SDOperand Mask) const; bool LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest, SmallPtrSet<SDNode*, 32> &NodesLeadingTo); @@ -205,20 +205,14 @@ private: SDOperand ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, bool isSigned, SDOperand &Hi); - SDOperand ExpandIntToFP(bool isSigned, MVT::ValueType DestTy, - SDOperand Source); + SDOperand ExpandIntToFP(bool isSigned, MVT DestTy, SDOperand Source); - SDOperand EmitStackConvert(SDOperand SrcOp, MVT::ValueType SlotVT, - MVT::ValueType DestVT); + SDOperand EmitStackConvert(SDOperand SrcOp, MVT SlotVT, MVT DestVT); SDOperand ExpandBUILD_VECTOR(SDNode *Node); SDOperand ExpandSCALAR_TO_VECTOR(SDNode *Node); - SDOperand ExpandLegalINT_TO_FP(bool isSigned, - SDOperand LegalOp, - MVT::ValueType DestVT); - SDOperand PromoteLegalINT_TO_FP(SDOperand LegalOp, MVT::ValueType DestVT, - bool isSigned); - SDOperand PromoteLegalFP_TO_INT(SDOperand LegalOp, MVT::ValueType DestVT, - bool isSigned); + SDOperand ExpandLegalINT_TO_FP(bool isSigned, SDOperand LegalOp, MVT DestVT); + SDOperand PromoteLegalINT_TO_FP(SDOperand LegalOp, MVT DestVT, bool isSigned); + SDOperand PromoteLegalFP_TO_INT(SDOperand LegalOp, MVT DestVT, bool isSigned); SDOperand ExpandBSWAP(SDOperand Op); SDOperand ExpandBitCount(unsigned Opc, SDOperand Op); @@ -238,8 +232,7 @@ private: /// /// Note that this will also return true for shuffles that are promoted to a /// different type. -SDNode *SelectionDAGLegalize::isShuffleLegal(MVT::ValueType VT, - SDOperand Mask) const { +SDNode *SelectionDAGLegalize::isShuffleLegal(MVT VT, SDOperand Mask) const { switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE, VT)) { default: return 0; case TargetLowering::Legal: @@ -248,11 +241,11 @@ SDNode *SelectionDAGLegalize::isShuffleLegal(MVT::ValueType VT, case TargetLowering::Promote: { // If this is promoted to a different type, convert the shuffle mask and // ask if it is legal in the promoted type! - MVT::ValueType NVT = TLI.getTypeToPromoteTo(ISD::VECTOR_SHUFFLE, VT); + MVT NVT = TLI.getTypeToPromoteTo(ISD::VECTOR_SHUFFLE, VT); // If we changed # elements, change the shuffle mask. unsigned NumEltsGrowth = - MVT::getVectorNumElements(NVT) / MVT::getVectorNumElements(VT); + NVT.getVectorNumElements() / VT.getVectorNumElements(); assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!"); if (NumEltsGrowth > 1) { // Renumber the elements. @@ -458,20 +451,20 @@ bool SelectionDAGLegalize::LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest, /// HandleOp - Legalize, Promote, or Expand the specified operand as /// appropriate for its type. void SelectionDAGLegalize::HandleOp(SDOperand Op) { - MVT::ValueType VT = Op.getValueType(); + MVT VT = Op.getValueType(); switch (getTypeAction(VT)) { default: assert(0 && "Bad type action!"); case Legal: (void)LegalizeOp(Op); break; case Promote: (void)PromoteOp(Op); break; case Expand: - if (!MVT::isVector(VT)) { + if (!VT.isVector()) { // If this is an illegal scalar, expand it into its two component // pieces. SDOperand X, Y; if (Op.getOpcode() == ISD::TargetConstant) break; // Allow illegal target nodes. ExpandOp(Op, X, Y); - } else if (MVT::getVectorNumElements(VT) == 1) { + } else if (VT.getVectorNumElements() == 1) { // If this is an illegal single element vector, convert it to a // scalar operation. (void)ScalarizeVectorOp(Op); @@ -497,7 +490,7 @@ static SDOperand ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP, // double. This shrinks FP constants and canonicalizes them for targets where // an FP extending load is the same cost as a normal load (such as on the x87 // fp stack or PPC FP unit). - MVT::ValueType VT = CFP->getValueType(0); + MVT VT = CFP->getValueType(0); ConstantFP *LLVMC = ConstantFP::get(CFP->getValueAPF()); if (!UseCP) { if (VT!=MVT::f64 && VT!=MVT::f32) @@ -506,16 +499,16 @@ static SDOperand ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP, (VT == MVT::f64) ? MVT::i64 : MVT::i32); } - MVT::ValueType OrigVT = VT; - MVT::ValueType SVT = VT; + MVT OrigVT = VT; + MVT SVT = VT; while (SVT != MVT::f32) { - SVT = (unsigned)SVT - 1; + SVT = (MVT::SimpleValueType)(SVT.getSimpleVT() - 1); if (CFP->isValueValidForType(SVT, CFP->getValueAPF()) && // Only do this if the target has a native EXTLOAD instruction from // smaller type. TLI.isLoadXLegal(ISD::EXTLOAD, SVT) && TLI.ShouldShrinkFPConstant(OrigVT)) { - const Type *SType = MVT::getTypeForValueType(SVT); + const Type *SType = SVT.getTypeForMVT(); LLVMC = cast<ConstantFP>(ConstantExpr::getFPTrunc(LLVMC, SType)); VT = SVT; Extend = true; @@ -535,13 +528,13 @@ static SDOperand ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP, /// ExpandFCOPYSIGNToBitwiseOps - Expands fcopysign to a series of bitwise /// operations. static -SDOperand ExpandFCOPYSIGNToBitwiseOps(SDNode *Node, MVT::ValueType NVT, +SDOperand ExpandFCOPYSIGNToBitwiseOps(SDNode *Node, MVT NVT, SelectionDAG &DAG, TargetLowering &TLI) { - MVT::ValueType VT = Node->getValueType(0); - MVT::ValueType SrcVT = Node->getOperand(1).getValueType(); + MVT VT = Node->getValueType(0); + MVT SrcVT = Node->getOperand(1).getValueType(); assert((SrcVT == MVT::f32 || SrcVT == MVT::f64) && "fcopysign expansion only supported for f32 and f64"); - MVT::ValueType SrcNVT = (SrcVT == MVT::f64) ? MVT::i64 : MVT::i32; + MVT SrcNVT = (SrcVT == MVT::f64) ? MVT::i64 : MVT::i32; // First get the sign bit of second operand. SDOperand Mask1 = (SrcVT == MVT::f64) @@ -551,7 +544,7 @@ SDOperand ExpandFCOPYSIGNToBitwiseOps(SDNode *Node, MVT::ValueType NVT, SDOperand SignBit= DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Node->getOperand(1)); SignBit = DAG.getNode(ISD::AND, SrcNVT, SignBit, Mask1); // Shift right or sign-extend it if the two operands have different types. - int SizeDiff = MVT::getSizeInBits(SrcNVT) - MVT::getSizeInBits(NVT); + int SizeDiff = SrcNVT.getSizeInBits() - NVT.getSizeInBits(); if (SizeDiff > 0) { SignBit = DAG.getNode(ISD::SRL, SrcNVT, SignBit, DAG.getConstant(SizeDiff, TLI.getShiftAmountTy())); @@ -579,17 +572,17 @@ SDOperand ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG, SDOperand Chain = ST->getChain(); SDOperand Ptr = ST->getBasePtr(); SDOperand Val = ST->getValue(); - MVT::ValueType VT = Val.getValueType(); + MVT VT = Val.getValueType(); int Alignment = ST->getAlignment(); int SVOffset = ST->getSrcValueOffset(); - if (MVT::isFloatingPoint(ST->getMemoryVT()) || - MVT::isVector(ST->getMemoryVT())) { + if (ST->getMemoryVT().isFloatingPoint() || + ST->getMemoryVT().isVector()) { // Expand to a bitconvert of the value to the integer type of the // same size, then a (misaligned) int store. - MVT::ValueType intVT; - if (MVT::is128BitVector(VT) || VT == MVT::ppcf128 || VT == MVT::f128) + MVT intVT; + if (VT.is128BitVector() || VT == MVT::ppcf128 || VT == MVT::f128) intVT = MVT::i128; - else if (MVT::is64BitVector(VT) || VT==MVT::f64) + else if (VT.is64BitVector() || VT==MVT::f64) intVT = MVT::i64; else if (VT==MVT::f32) intVT = MVT::i32; @@ -600,12 +593,13 @@ SDOperand ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG, return DAG.getStore(Chain, Result, Ptr, ST->getSrcValue(), SVOffset, ST->isVolatile(), Alignment); } - assert(MVT::isInteger(ST->getMemoryVT()) && - !MVT::isVector(ST->getMemoryVT()) && + assert(ST->getMemoryVT().isInteger() && + !ST->getMemoryVT().isVector() && "Unaligned store of unknown type."); // Get the half-size VT - MVT::ValueType NewStoredVT = ST->getMemoryVT() - 1; - int NumBits = MVT::getSizeInBits(NewStoredVT); + MVT NewStoredVT = + (MVT::SimpleValueType)(ST->getMemoryVT().getSimpleVT() - 1); + int NumBits = NewStoredVT.getSizeInBits(); int IncrementSize = NumBits / 8; // Divide the stored value in two parts. @@ -635,16 +629,16 @@ SDOperand ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG, int SVOffset = LD->getSrcValueOffset(); SDOperand Chain = LD->getChain(); SDOperand Ptr = LD->getBasePtr(); - MVT::ValueType VT = LD->getValueType(0); - MVT::ValueType LoadedVT = LD->getMemoryVT(); - if (MVT::isFloatingPoint(VT) || MVT::isVector(VT)) { + MVT VT = LD->getValueType(0); + MVT LoadedVT = LD->getMemoryVT(); + if (VT.isFloatingPoint() || VT.isVector()) { // Expand to a (misaligned) integer load of the same size, // then bitconvert to floating point or vector. - MVT::ValueType intVT; - if (MVT::is128BitVector(LoadedVT) || + MVT intVT; + if (LoadedVT.is128BitVector() || LoadedVT == MVT::ppcf128 || LoadedVT == MVT::f128) intVT = MVT::i128; - else if (MVT::is64BitVector(LoadedVT) || LoadedVT == MVT::f64) + else if (LoadedVT.is64BitVector() || LoadedVT == MVT::f64) intVT = MVT::i64; else if (LoadedVT == MVT::f32) intVT = MVT::i32; @@ -655,21 +649,21 @@ SDOperand ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG, SVOffset, LD->isVolatile(), LD->getAlignment()); SDOperand Result = DAG.getNode(ISD::BIT_CONVERT, LoadedVT, newLoad); - if (MVT::isFloatingPoint(VT) && LoadedVT != VT) + if (VT.isFloatingPoint() && LoadedVT != VT) Result = DAG.getNode(ISD::FP_EXTEND, VT, Result); SDOperand Ops[] = { Result, Chain }; return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other), Ops, 2); } - assert(MVT::isInteger(LoadedVT) && !MVT::isVector(LoadedVT) && + assert(LoadedVT.isInteger() && !LoadedVT.isVector() && "Unaligned load of unsupported type."); // Compute the new VT that is half the size of the old one. This is an // integer MVT. - unsigned NumBits = MVT::getSizeInBits(LoadedVT); - MVT::ValueType NewLoadedVT; - NewLoadedVT = MVT::getIntegerType(NumBits/2); + unsigned NumBits = LoadedVT.getSizeInBits(); + MVT NewLoadedVT; + NewLoadedVT = MVT::getIntegerVT(NumBits/2); NumBits >>= 1; unsigned Alignment = LD->getAlignment(); @@ -717,23 +711,23 @@ SDOperand ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG, /// no way of lowering. "Unroll" the vector, splitting out the scalars and /// operating on each element individually. SDOperand SelectionDAGLegalize::UnrollVectorOp(SDOperand Op) { - MVT::ValueType VT = Op.getValueType(); + MVT VT = Op.getValueType(); assert(isTypeLegal(VT) && "Caller should expand or promote operands that are not legal!"); assert(Op.Val->getNumValues() == 1 && "Can't unroll a vector with multiple results!"); - unsigned NE = MVT::getVectorNumElements(VT); - MVT::ValueType EltVT = MVT::getVectorElementType(VT); + unsigned NE = VT.getVectorNumElements(); + MVT EltVT = VT.getVectorElementType(); SmallVector<SDOperand, 8> Scalars; SmallVector<SDOperand, 4> Operands(Op.getNumOperands()); for (unsigned i = 0; i != NE; ++i) { for (unsigned j = 0; j != Op.getNumOperands(); ++j) { SDOperand Operand = Op.getOperand(j); - MVT::ValueType OperandVT = Operand.getValueType(); - if (MVT::isVector(OperandVT)) { + MVT OperandVT = Operand.getValueType(); + if (OperandVT.isVector()) { // A vector operand; extract a single element. - MVT::ValueType OperandEltVT = MVT::getVectorElementType(OperandVT); + MVT OperandEltVT = OperandVT.getVectorElementType(); Operands[j] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, OperandEltVT, Operand, @@ -751,7 +745,7 @@ SDOperand SelectionDAGLegalize::UnrollVectorOp(SDOperand Op) { } /// GetFPLibCall - Return the right libcall for the given floating point type. -static RTLIB::Libcall GetFPLibCall(MVT::ValueType VT, +static RTLIB::Libcall GetFPLibCall(MVT VT, RTLIB::Libcall Call_F32, RTLIB::Libcall Call_F64, RTLIB::Libcall Call_F80, @@ -780,10 +774,10 @@ PerformInsertVectorEltInMemory(SDOperand Vec, SDOperand Val, SDOperand Idx) { // with a "move to register" or "extload into register" instruction, then // permute it into place, if the idx is a constant and if the idx is // supported by the target. - MVT::ValueType VT = Tmp1.getValueType(); - MVT::ValueType EltVT = MVT::getVectorElementType(VT); - MVT::ValueType IdxVT = Tmp3.getValueType(); - MVT::ValueType PtrVT = TLI.getPointerTy(); + MVT VT = Tmp1.getValueType(); + MVT EltVT = VT.getVectorElementType(); + MVT IdxVT = Tmp3.getValueType(); + MVT PtrVT = TLI.getPointerTy(); SDOperand StackPtr = DAG.CreateStackTemporary(VT); FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(StackPtr.Val); @@ -798,7 +792,7 @@ PerformInsertVectorEltInMemory(SDOperand Vec, SDOperand Val, SDOperand Idx) { unsigned CastOpc = (IdxVT > PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND; Tmp3 = DAG.getNode(CastOpc, PtrVT, Tmp3); // Add the offset to the index. - unsigned EltSize = MVT::getSizeInBits(EltVT)/8; + unsigned EltSize = EltVT.getSizeInBits()/8; Tmp3 = DAG.getNode(ISD::MUL, IdxVT, Tmp3,DAG.getConstant(EltSize, IdxVT)); SDOperand StackPtr2 = DAG.getNode(ISD::ADD, IdxVT, Tmp3, StackPtr); // Store the scalar value. @@ -911,7 +905,7 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { Result = DAG.getConstant(0, TLI.getPointerTy()); break; case ISD::FRAME_TO_ARGS_OFFSET: { - MVT::ValueType VT = Node->getValueType(0); + MVT VT = Node->getValueType(0); switch (TLI.getOperationAction(Node->getOpcode(), VT)) { default: assert(0 && "This action is not supported yet!"); case TargetLowering::Custom: @@ -926,7 +920,7 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { break; case ISD::EXCEPTIONADDR: { Tmp1 = LegalizeOp(Node->getOperand(0)); - MVT::ValueType VT = Node->getValueType(0); + MVT VT = Node->getValueType(0); switch (TLI.getOperationAction(Node->getOpcode(), VT)) { default: assert(0 && "This action is not supported yet!"); case TargetLowering::Expand: { @@ -961,7 +955,7 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { case ISD::EHSELECTION: { Tmp1 = LegalizeOp(Node->getOperand(0)); Tmp2 = LegalizeOp(Node->getOperand(1)); - MVT::ValueType VT = Node->getValueType(0); + MVT VT = Node->getValueType(0); switch (TLI.getOperationAction(Node->getOpcode(), VT)) { default: assert(0 && "This action is not supported yet!"); case TargetLowering::Expand: { @@ -994,7 +988,7 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { AddLegalizedOperand(Op.getValue(1), Tmp2); return Op.ResNo ? Tmp2 : Tmp1; case ISD::EH_RETURN: { - MVT::ValueType VT = Node->getValueType(0); + MVT VT = Node->getValueType(0); // The only "good" option for this node is to custom lower it. switch (TLI.getOperationAction(Node->getOpcode(), VT)) { default: assert(0 && "This action is not supported at all!"); @@ -1039,14 +1033,14 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { AddLegalizedOperand(Op.getValue(1), Result.getValue(1)); return Result.getValue(Op.ResNo); case ISD::UNDEF: { - MVT::ValueType VT = Op.getValueType(); + MVT VT = Op.getValueType(); switch (TLI.getOperationAction(ISD::UNDEF, VT)) { default: assert(0 && "This action is not supported yet!"); case TargetLowering::Expand: - if (MVT::isInteger(VT)) + if (VT.isInteger()) Result = DAG.getConstant(0, VT); - else if (MVT::isFloatingPoint(VT)) - Result = DAG.getConstantFP(APFloat(APInt(MVT::getSizeInBits(VT), 0)), + else if (VT.isFloatingPoint()) + Result = DAG.getConstantFP(APFloat(APInt(VT.getSizeInBits(), 0)), VT); else assert(0 && "Unknown value type!"); @@ -1454,13 +1448,14 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { // SCALAR_TO_VECTOR requires that the type of the value being inserted // match the element type of the vector being created. if (Tmp2.getValueType() == - MVT::getVectorElementType(Op.getValueType())) { + Op.getValueType().getVectorElementType()) { SDOperand ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, Tmp1.getValueType(), Tmp2); - unsigned NumElts = MVT::getVectorNumElements(Tmp1.getValueType()); - MVT::ValueType ShufMaskVT = MVT::getIntVectorWithNumElements(NumElts); - MVT::ValueType ShufMaskEltVT = MVT::getVectorElementType(ShufMaskVT); + unsigned NumElts = Tmp1.getValueType().getVectorNumElements(); + MVT ShufMaskVT = + MVT::getIntVectorWithNumElements(NumElts); + MVT ShufMaskEltVT = ShufMaskVT.getVectorElementType(); // We generate a shuffle of InVec and ScVec, so the shuffle mask // should be 0,1,2,3,4,5... with the appropriate element replaced with @@ -1531,9 +1526,9 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { } // FALLTHROUGH case TargetLowering::Expand: { - MVT::ValueType VT = Node->getValueType(0); - MVT::ValueType EltVT = MVT::getVectorElementType(VT); - MVT::ValueType PtrVT = TLI.getPointerTy(); + MVT VT = Node->getValueType(0); + MVT EltVT = VT.getVectorElementType(); + MVT PtrVT = TLI.getPointerTy(); SDOperand Mask = Node->getOperand(2); unsigned NumElems = Mask.getNumOperands(); SmallVector<SDOperand,8> Ops; @@ -1557,8 +1552,8 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { } case TargetLowering::Promote: { // Change base type to a different vector type. - MVT::ValueType OVT = Node->getValueType(0); - MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); + MVT OVT = Node->getValueType(0); + MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); // Cast the two input vectors. Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1); @@ -1679,7 +1674,7 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); return Result.getValue(Op.ResNo); case ISD::DYNAMIC_STACKALLOC: { - MVT::ValueType VT = Node->getValueType(0); + MVT VT = Node->getValueType(0); Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the size. Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the alignment. @@ -1820,7 +1815,7 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { SDOperand Table = Result.getOperand(1); SDOperand Index = Result.getOperand(2); - MVT::ValueType PTy = TLI.getPointerTy(); + MVT PTy = TLI.getPointerTy(); MachineFunction &MF = DAG.getMachineFunction(); unsigned EntrySize = MF.getJumpTableInfo()->getEntrySize(); Index= DAG.getNode(ISD::MUL, PTy, Index, DAG.getConstant(EntrySize, PTy)); @@ -1939,7 +1934,7 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { ISD::LoadExtType ExtType = LD->getExtensionType(); if (ExtType == ISD::NON_EXTLOAD) { - MVT::ValueType VT = Node->getValueType(0); + MVT VT = Node->getValueType(0); Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset()); Tmp3 = Result.getValue(0); Tmp4 = Result.getValue(1); @@ -1951,7 +1946,7 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { // expand it. if (!TLI.allowsUnalignedMemoryAccesses()) { unsigned ABIAlignment = TLI.getTargetData()-> - getABITypeAlignment(MVT::getTypeForValueType(LD->getMemoryVT())); + getABITypeAlignment(LD->getMemoryVT().getTypeForMVT()); if (LD->getAlignment() < ABIAlignment){ Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.Val), DAG, TLI); @@ -1971,9 +1966,9 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { break; case TargetLowering::Promote: { // Only promote a load of vector type to another. - assert(MVT::isVector(VT) && "Cannot promote this load!"); + assert(VT.isVector() && "Cannot promote this load!"); // Change base type to a different vector type. - MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT); + MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT); Tmp1 = DAG.getLoad(NVT, Tmp1, Tmp2, LD->getSrcValue(), LD->getSrcValueOffset(), @@ -1989,13 +1984,13 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { AddLegalizedOperand(SDOperand(Node, 1), Tmp4); return Op.ResNo ? Tmp4 : Tmp3; } else { - MVT::ValueType SrcVT = LD->getMemoryVT(); - unsigned SrcWidth = MVT::getSizeInBits(SrcVT); + MVT SrcVT = LD->getMemoryVT(); + unsigned SrcWidth = SrcVT.getSizeInBits(); int SVOffset = LD->getSrcValueOffset(); unsigned Alignment = LD->getAlignment(); bool isVolatile = LD->isVolatile(); - if (SrcWidth != MVT::getStoreSizeInBits(SrcVT) && + if (SrcWidth != SrcVT.getStoreSizeInBits() && // Some targets pretend to have an i1 loading operation, and actually // load an i8. This trick is correct for ZEXTLOAD because the top 7 // bits are guaranteed to be zero; it helps the optimizers understand @@ -2007,8 +2002,8 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { TLI.getLoadXAction(ExtType, MVT::i1) == TargetLowering::Promote)) { // Promote to a byte-sized load if not loading an integral number of // bytes. For example, promote EXTLOAD:i20 -> EXTLOAD:i24. - unsigned NewWidth = MVT::getStoreSizeInBits(SrcVT); - MVT::ValueType NVT = MVT::getIntegerType(NewWidth); + unsigned NewWidth = SrcVT.getStoreSizeInBits(); + MVT NVT = MVT::getIntegerVT(NewWidth); SDOperand Ch; // The extra bits are guaranteed to be zero, since we stored them that @@ -2036,7 +2031,7 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { Tmp2 = LegalizeOp(Ch); } else if (SrcWidth & (SrcWidth - 1)) { // If not loading a power-of-2 number of bits, expand as two loads. - assert(MVT::isExtendedVT(SrcVT) && !MVT::isVector(SrcVT) && + assert(SrcVT.isExtended() && !SrcVT.isVector() && "Unsupported extload!"); unsigned RoundWidth = 1 << Log2_32(SrcWidth); assert(RoundWidth < SrcWidth); @@ -2044,8 +2039,8 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { assert(ExtraWidth < RoundWidth); assert(!(RoundWidth % 8) && !(ExtraWidth % 8) && "Load size not an integral number of bytes!"); - MVT::ValueType RoundVT = MVT::getIntegerType(RoundWidth); - MVT::ValueType ExtraVT = MVT::getIntegerType(ExtraWidth); + MVT RoundVT = MVT::getIntegerVT(RoundWidth); + MVT ExtraVT = MVT::getIntegerVT(ExtraWidth); SDOperand Lo, Hi, Ch; unsigned IncrementSize; @@ -2130,7 +2125,7 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { // expand it. if (!TLI.allowsUnalignedMemoryAccesses()) { unsigned ABIAlignment = TLI.getTargetData()-> - getABITypeAlignment(MVT::getTypeForValueType(LD->getMemoryVT())); + getABITypeAlignment(LD->getMemoryVT().getTypeForMVT()); if (LD->getAlignment() < ABIAlignment){ Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.Val), DAG, TLI); @@ -2180,14 +2175,14 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { } } case ISD::EXTRACT_ELEMENT: { - MVT::ValueType OpTy = Node->getOperand(0).getValueType(); + MVT OpTy = Node->getOperand(0).getValueType(); switch (getTypeAction(OpTy)) { default: assert(0 && "EXTRACT_ELEMENT action for type unimplemented!"); case Legal: if (cast<ConstantSDNode>(Node->getOperand(1))->getValue()) { // 1 -> Hi Result = DAG.getNode(ISD::SRL, OpTy, Node->getOperand(0), - DAG.getConstant(MVT::getSizeInBits(OpTy)/2, + DAG.getConstant(OpTy.getSizeInBits()/2, TLI.getShiftAmountTy())); Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Result); } else { @@ -2252,7 +2247,7 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { Result = DAG.UpdateNodeOperands(Result, Tmp1, LegalizeOp(Tmp2), Tmp3); break; case Expand: - if (!MVT::isVector(Tmp2.getValueType())) { + if (!Tmp2.getValueType().isVector()) { SDOperand Lo, Hi; ExpandOp(Tmp2, Lo, Hi); @@ -2268,12 +2263,12 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { } else { SDNode *InVal = Tmp2.Val; int InIx = Tmp2.ResNo; - unsigned NumElems = MVT::getVectorNumElements(InVal->getValueType(InIx)); - MVT::ValueType EVT = MVT::getVectorElementType(InVal->getValueType(InIx)); + unsigned NumElems = InVal->getValueType(InIx).getVectorNumElements(); + MVT EVT = InVal->getValueType(InIx).getVectorElementType(); // Figure out if there is a simple type corresponding to this Vector // type. If so, convert to the vector type. - MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems); + MVT TVT = MVT::getVectorVT(EVT, NumElems); if (TLI.isTypeLegal(TVT)) { // Turn this into a return of the vector type. Tmp2 = LegalizeOp(Tmp2); @@ -2321,7 +2316,7 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { break; case Expand: { SDOperand Lo, Hi; - assert(!MVT::isExtendedVT(Node->getOperand(i).getValueType()) && + assert(!Node->getOperand(i).getValueType().isExtended() && "FIXME: TODO: implement returning non-legal vector types!"); ExpandOp(Node->getOperand(i), Lo, Hi); NewValues.push_back(Lo); @@ -2417,7 +2412,7 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2, ST->getOffset()); - MVT::ValueType VT = Tmp3.getValueType(); + MVT VT = Tmp3.getValueType(); switch (TLI.getOperationAction(ISD::STORE, VT)) { default: assert(0 && "This action is not supported yet!"); case TargetLowering::Legal: @@ -2425,7 +2420,7 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { // expand it. if (!TLI.allowsUnalignedMemoryAccesses()) { unsigned ABIAlignment = TLI.getTargetData()-> - getABITypeAlignment(MVT::getTypeForValueType(ST->getMemoryVT())); + getABITypeAlignment(ST->getMemoryVT().getTypeForMVT()); if (ST->getAlignment() < ABIAlignment) Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.Val), DAG, TLI); @@ -2436,7 +2431,7 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { if (Tmp1.Val) Result = Tmp1; break; case TargetLowering::Promote: - assert(MVT::isVector(VT) && "Unknown legal promote case!"); + assert(VT.isVector() && "Unknown legal promote case!"); Tmp3 = DAG.getNode(ISD::BIT_CONVERT, TLI.getTypeToPromoteTo(ISD::STORE, VT), Tmp3); Result = DAG.getStore(Tmp1, Tmp3, Tmp2, @@ -2461,16 +2456,16 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { // If this is a vector type, then we have to calculate the increment as // the product of the element size in bytes, and the number of elements // in the high half of the vector. - if (MVT::isVector(ST->getValue().getValueType())) { + if (ST->getValue().getValueType().isVector()) { SDNode *InVal = ST->getValue().Val; int InIx = ST->getValue().ResNo; - MVT::ValueType InVT = InVal->getValueType(InIx); - unsigned NumElems = MVT::getVectorNumElements(InVT); - MVT::ValueType EVT = MVT::getVectorElementType(InVT); + MVT InVT = InVal->getValueType(InIx); + unsigned NumElems = InVT.getVectorNumElements(); + MVT EVT = InVT.getVectorElementType(); // Figure out if there is a simple type corresponding to this Vector // type. If so, convert to the vector type. - MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems); + MVT TVT = MVT::getVectorVT(EVT, NumElems); if (TLI.isTypeLegal(TVT)) { // Turn this into a normal store of the vector type. Tmp3 = LegalizeOp(ST->getValue()); @@ -2489,12 +2484,12 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { break; } else { SplitVectorOp(ST->getValue(), Lo, Hi); - IncrementSize = MVT::getVectorNumElements(Lo.Val->getValueType(0)) * - MVT::getSizeInBits(EVT)/8; + IncrementSize = Lo.Val->getValueType(0).getVectorNumElements() * + EVT.getSizeInBits()/8; } } else { ExpandOp(ST->getValue(), Lo, Hi); - IncrementSize = Hi.Val ? MVT::getSizeInBits(Hi.getValueType())/8 : 0; + IncrementSize = Hi.Val ? Hi.getValueType().getSizeInBits()/8 : 0; if (TLI.isBigEndian()) std::swap(Lo, Hi); @@ -2537,20 +2532,20 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { SVOffset, MVT::i8, isVolatile, Alignment); } - MVT::ValueType StVT = ST->getMemoryVT(); - unsigned StWidth = MVT::getSizeInBits(StVT); + MVT StVT = ST->getMemoryVT(); + unsigned StWidth = StVT.getSizeInBits(); - if (StWidth != MVT::getStoreSizeInBits(StVT)) { + if (StWidth != StVT.getStoreSizeInBits()) { // Promote to a byte-sized store with upper bits zero if not // storing an integral number of bytes. For example, promote // TRUNCSTORE:i1 X -> TRUNCSTORE:i8 (and X, 1) - MVT::ValueType NVT = MVT::getIntegerType(MVT::getStoreSizeInBits(StVT)); + MVT NVT = MVT::getIntegerVT(StVT.getStoreSizeInBits()); Tmp3 = DAG.getZeroExtendInReg(Tmp3, StVT); Result = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), SVOffset, NVT, isVolatile, Alignment); } else if (StWidth & (StWidth - 1)) { // If not storing a power-of-2 number of bits, expand as two stores. - assert(MVT::isExtendedVT(StVT) && !MVT::isVector(StVT) && + assert(StVT.isExtended() && !StVT.isVector() && "Unsupported truncstore!"); unsigned RoundWidth = 1 << Log2_32(StWidth); assert(RoundWidth < StWidth); @@ -2558,8 +2553,8 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { assert(ExtraWidth < RoundWidth); assert(!(RoundWidth % 8) && !(ExtraWidth % 8) && "Store size not an integral number of bytes!"); - MVT::ValueType RoundVT = MVT::getIntegerType(RoundWidth); - MVT::ValueType ExtraVT = MVT::getIntegerType(ExtraWidth); + MVT RoundVT = MVT::getIntegerVT(RoundWidth); + MVT ExtraVT = MVT::getIntegerVT(ExtraWidth); SDOperand Lo, Hi; unsigned IncrementSize; @@ -2612,7 +2607,7 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { // expand it. if (!TLI.allowsUnalignedMemoryAccesses()) { unsigned ABIAlignment = TLI.getTargetData()-> - getABITypeAlignment(MVT::getTypeForValueType(ST->getMemoryVT())); + getABITypeAlignment(ST->getMemoryVT().getTypeForMVT()); if (ST->getAlignment() < ABIAlignment) Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.Val), DAG, TLI); @@ -2761,13 +2756,13 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { } break; case TargetLowering::Promote: { - MVT::ValueType NVT = + MVT NVT = TLI.getTypeToPromoteTo(ISD::SELECT, Tmp2.getValueType()); unsigned ExtOp, TruncOp; - if (MVT::isVector(Tmp2.getValueType())) { + if (Tmp2.getValueType().isVector()) { ExtOp = ISD::BIT_CONVERT; TruncOp = ISD::BIT_CONVERT; - } else if (MVT::isInteger(Tmp2.getValueType())) { + } else if (Tmp2.getValueType().isInteger()) { ExtOp = ISD::ANY_EXTEND; TruncOp = ISD::TRUNCATE; } else { @@ -2847,23 +2842,23 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { // First step, figure out the appropriate operation to use. // Allow SETCC to not be supported for all legal data types // Mostly this targets FP - MVT::ValueType NewInTy = Node->getOperand(0).getValueType(); - MVT::ValueType OldVT = NewInTy; OldVT = OldVT; + MVT NewInTy = Node->getOperand(0).getValueType(); + MVT OldVT = NewInTy; OldVT = OldVT; // Scan for the appropriate larger type to use. while (1) { - NewInTy = (MVT::ValueType)(NewInTy+1); + NewInTy = (MVT::SimpleValueType)(NewInTy.getSimpleVT()+1); - assert(MVT::isInteger(NewInTy) == MVT::isInteger(OldVT) && + assert(NewInTy.isInteger() == OldVT.isInteger() && "Fell off of the edge of the integer world"); - assert(MVT::isFloatingPoint(NewInTy) == MVT::isFloatingPoint(OldVT) && + assert(NewInTy.isFloatingPoint() == OldVT.isFloatingPoint() && "Fell off of the edge of the floating point world"); // If the target supports SETCC of this type, use it. if (TLI.isOperationLegal(ISD::SETCC, NewInTy)) break; } - if (MVT::isInteger(NewInTy)) + if (NewInTy.isInteger()) assert(0 && "Cannot promote Legal Integer SETCC yet"); else { Tmp1 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp1); @@ -2878,7 +2873,7 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { case TargetLowering::Expand: // Expand a setcc node into a select_cc of the same condition, lhs, and // rhs that selects between const 1 (true) and const 0 (false). - MVT::ValueType VT = Node->getValueType(0); + MVT VT = Node->getValueType(0); Result = DAG.getNode(ISD::SELECT_CC, VT, Tmp1, Tmp2, DAG.getConstant(1, VT), DAG.getConstant(0, VT), Tmp3); @@ -2983,7 +2978,7 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { if (Tmp1.Val) Result = Tmp1; break; case TargetLowering::Expand: { - MVT::ValueType VT = Op.getValueType(); + MVT VT = Op.getValueType(); // See if multiply or divide can be lowered using two-result operations. SDVTList VTs = DAG.getVTList(VT, VT); @@ -3056,7 +3051,7 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { break; } - assert(MVT::isVector(Node->getValueType(0)) && + assert(Node->getValueType(0).isVector() && "Cannot expand this binary operator!"); // Expand the operation into a bunch of nasty scalar code. Result = LegalizeOp(UnrollVectorOp(Op)); @@ -3068,9 +3063,9 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { case ISD::AND: case ISD::OR: case ISD::XOR: { - MVT::ValueType OVT = Node->getValueType(0); - MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); - assert(MVT::isVector(OVT) && "Cannot promote this BinOp!"); + MVT OVT = Node->getValueType(0); + MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); + assert(OVT.isVector() && "Cannot promote this BinOp!"); // Bit convert each of the values to the new type. Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1); Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2); @@ -3128,7 +3123,7 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { TLI.getOperationAction(ISD::FNEG, Tmp1.getValueType()) == TargetLowering::Legal) { // Get the sign bit of the RHS. - MVT::ValueType IVT = + MVT IVT = Tmp2.getValueType() == MVT::f32 ? MVT::i32 : MVT::i64; SDOperand SignBit = DAG.getNode(ISD::BIT_CONVERT, IVT, Tmp2); SignBit = DAG.getSetCC(TLI.getSetCCResultType(SignBit), @@ -3146,7 +3141,7 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { } // Otherwise, do bitwise ops! - MVT::ValueType NVT = + MVT NVT = Node->getValueType(0) == MVT::f32 ? MVT::i32 : MVT::i64; Result = ExpandFCOPYSIGNToBitwiseOps(Node, NVT, DAG, TLI); Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0), Result); @@ -3180,7 +3175,7 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { return Result; case ISD::BUILD_PAIR: { - MVT::ValueType PairTy = Node->getValueType(0); + MVT PairTy = Node->getValueType(0); // TODO: handle the case where the Lo and Hi operands are not of legal type Tmp1 = LegalizeOp(Node->getOperand(0)); // Lo Tmp2 = LegalizeOp(Node->getOperand(1)); // Hi @@ -3196,7 +3191,7 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, PairTy, Tmp1); Tmp2 = DAG.getNode(ISD::ANY_EXTEND, PairTy, Tmp2); Tmp2 = DAG.getNode(ISD::SHL, PairTy, Tmp2, - DAG.getConstant(MVT::getSizeInBits(PairTy)/2, + DAG.getConstant(PairTy.getSizeInBits()/2, TLI.getShiftAmountTy())); Result = DAG.getNode(ISD::OR, PairTy, Tmp1, Tmp2); break; @@ -3225,7 +3220,7 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { case TargetLowering::Expand: { unsigned DivOpc= (Node->getOpcode() == ISD::UREM) ? ISD::UDIV : ISD::SDIV; bool isSigned = DivOpc == ISD::SDIV; - MVT::ValueType VT = Node->getValueType(0); + MVT VT = Node->getValueType(0); // See if remainder can be lowered using two-result operations. SDVTList VTs = DAG.getVTList(VT, VT); @@ -3240,14 +3235,14 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { break; } - if (MVT::isInteger(VT)) { + |