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-rw-r--r--include/llvm/IntrinsicsX86.td16
1 files changed, 15 insertions, 1 deletions
diff --git a/include/llvm/IntrinsicsX86.td b/include/llvm/IntrinsicsX86.td
index 3776f7db8f..1bd73f4a2d 100644
--- a/include/llvm/IntrinsicsX86.td
+++ b/include/llvm/IntrinsicsX86.td
@@ -133,7 +133,8 @@ let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
// SIMD store ops
let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
def int_x86_sse_storeu_ps : GCCBuiltin<"__builtin_ia32_storeups">,
- Intrinsic<[llvm_ptr_ty, llvm_v4f32_ty], [IntrWriteMem]>;
+ Intrinsic<[llvm_void_ty, llvm_ptr_ty,
+ llvm_v4f32_ty], [IntrWriteMem]>;
}
// Cacheability support ops
@@ -267,6 +268,19 @@ let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
llvm_int_ty], [InstrNoMem]>;
}
+// SIMD load ops
+let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
+ def int_x86_sse2_loadu_pd : GCCBuiltin<"__builtin_ia32_loadupd">,
+ Intrinsic<[llvm_v2f64_ty, llvm_ptr_ty], [IntrReadMem]>;
+}
+
+// SIMD store ops
+let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
+ def int_x86_sse2_storeu_pd : GCCBuiltin<"__builtin_ia32_storeupd">,
+ Intrinsic<[llvm_void_ty, llvm_ptr_ty,
+ llvm_v2f64_ty], [IntrWriteMem]>;
+}
+
// Misc.
let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
def int_x86_sse2_packsswb_128 : GCCBuiltin<"__builtin_ia32_packsswb128">,