diff options
53 files changed, 263 insertions, 196 deletions
diff --git a/include/llvm/CodeGen/MachineCodeEmitter.h b/include/llvm/CodeGen/MachineCodeEmitter.h index 987661597f..ece416c78d 100644 --- a/include/llvm/CodeGen/MachineCodeEmitter.h +++ b/include/llvm/CodeGen/MachineCodeEmitter.h @@ -18,8 +18,6 @@ #define LLVM_CODEGEN_MACHINECODEEMITTER_H #include "llvm/Support/DataTypes.h" -#include "llvm/Support/ErrorHandling.h" -#include "llvm/Support/raw_ostream.h" namespace llvm { diff --git a/include/llvm/CodeGen/SelectionDAGISel.h b/include/llvm/CodeGen/SelectionDAGISel.h index b98636aa6e..d2c0dc420f 100644 --- a/include/llvm/CodeGen/SelectionDAGISel.h +++ b/include/llvm/CodeGen/SelectionDAGISel.h @@ -19,8 +19,6 @@ #include "llvm/Pass.h" #include "llvm/Constant.h" #include "llvm/CodeGen/SelectionDAG.h" -#include "llvm/Support/ErrorHandling.h" -#include "llvm/Support/raw_ostream.h" namespace llvm { class FastISel; diff --git a/include/llvm/Support/ErrorHandling.h b/include/llvm/Support/ErrorHandling.h index 758d9243c0..c7e4297f00 100644 --- a/include/llvm/Support/ErrorHandling.h +++ b/include/llvm/Support/ErrorHandling.h @@ -49,7 +49,11 @@ namespace llvm { void llvm_unreachable(void) NORETURN; } -#define LLVM_UNREACHABLE(msg) do { assert(0 && msg); llvm_unreachable(); } while(0) +#ifndef NDEBUG +#define LLVM_UNREACHABLE(msg) do {cerr<<msg<<"\n";llvm_unreachable();}while(0) +#else +#define LLVM_UNREACHABLE(msg) llvm_unreachable() +#endif #endif diff --git a/lib/Target/ARM/ARMBaseRegisterInfo.cpp b/lib/Target/ARM/ARMBaseRegisterInfo.cpp index e51699baa4..2bf7e51d83 100644 --- a/lib/Target/ARM/ARMBaseRegisterInfo.cpp +++ b/lib/Target/ARM/ARMBaseRegisterInfo.cpp @@ -28,6 +28,7 @@ #include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/CodeGen/RegisterScavenging.h" #include "llvm/Support/ErrorHandling.h" +#include "llvm/Support/raw_ostream.h" #include "llvm/Target/TargetFrameInfo.h" #include "llvm/Target/TargetMachine.h" #include "llvm/Target/TargetOptions.h" diff --git a/lib/Target/ARM/ARMCodeEmitter.cpp b/lib/Target/ARM/ARMCodeEmitter.cpp index f436e97bcc..d43a76edc5 100644 --- a/lib/Target/ARM/ARMCodeEmitter.cpp +++ b/lib/Target/ARM/ARMCodeEmitter.cpp @@ -257,10 +257,10 @@ unsigned Emitter<CodeEmitter>::getMachineOpValue(const MachineInstr &MI, else if (MO.isMBB()) emitMachineBasicBlock(MO.getMBB(), ARM::reloc_arm_branch); else { - std::string msg; - raw_string_ostream Msg(msg); - Msg << "ERROR: Unknown type of MachineOperand: " << MO; - llvm_report_error(Msg.str()); +#ifndef NDEBUG + cerr << MO; +#endif + llvm_unreachable(); } return 0; } @@ -588,7 +588,7 @@ void Emitter<CodeEmitter>::emitPseudoInstruction(const MachineInstr &MI) { unsigned Opcode = MI.getDesc().Opcode; switch (Opcode) { default: - llvm_report_error("ARMCodeEmitter::emitPseudoInstruction");//FIXME: + LLVM_UNREACHABLE("ARMCodeEmitter::emitPseudoInstruction");//FIXME: case TargetInstrInfo::INLINEASM: { // We allow inline assembler nodes with empty bodies - they can // implicitly define registers, which is ok for JIT. @@ -1119,8 +1119,9 @@ template<class CodeEmitter> void Emitter<CodeEmitter>::emitBranchInstruction(const MachineInstr &MI) { const TargetInstrDesc &TID = MI.getDesc(); - if (TID.Opcode == ARM::TPsoft) - llvm_report_error("ARM::TPsoft FIXME"); // FIXME + if (TID.Opcode == ARM::TPsoft) { + LLVM_UNREACHABLE("ARM::TPsoft FIXME"); // FIXME + } // Part of binary is determined by TableGn. unsigned Binary = getBinaryCodeForInstr(MI); diff --git a/lib/Target/ARM/ARMISelDAGToDAG.cpp b/lib/Target/ARM/ARMISelDAGToDAG.cpp index 6d7e41cc35..71a6305900 100644 --- a/lib/Target/ARM/ARMISelDAGToDAG.cpp +++ b/lib/Target/ARM/ARMISelDAGToDAG.cpp @@ -30,6 +30,9 @@ #include "llvm/Target/TargetOptions.h" #include "llvm/Support/Compiler.h" #include "llvm/Support/Debug.h" +#include "llvm/Support/ErrorHandling.h" +#include "llvm/Support/raw_ostream.h" + using namespace llvm; static const unsigned arm_dsubreg_0 = 5; diff --git a/lib/Target/ARM/ARMJITInfo.cpp b/lib/Target/ARM/ARMJITInfo.cpp index bc28919817..c9e04c9506 100644 --- a/lib/Target/ARM/ARMJITInfo.cpp +++ b/lib/Target/ARM/ARMJITInfo.cpp @@ -123,12 +123,12 @@ extern "C" void ARMCompilationCallbackC(intptr_t StubAddr) { // ldr pc, [pc,#-4] // <addr> if (!sys::Memory::setRangeWritable((void*)StubAddr, 8)) { - llvm_report_error("ERROR: Unable to mark stub writable"); + LLVM_UNREACHABLE("ERROR: Unable to mark stub writable"); } *(intptr_t *)StubAddr = 0xe51ff004; // ldr pc, [pc, #-4] *(intptr_t *)(StubAddr+4) = NewVal; if (!sys::Memory::setRangeExecutable((void*)StubAddr, 8)) { - llvm_report_error("ERROR: Unable to mark stub executable"); + LLVM_UNREACHABLE("ERROR: Unable to mark stub executable"); } } diff --git a/lib/Target/ARM/ARMLoadStoreOptimizer.cpp b/lib/Target/ARM/ARMLoadStoreOptimizer.cpp index d9e21b8e07..67c4258046 100644 --- a/lib/Target/ARM/ARMLoadStoreOptimizer.cpp +++ b/lib/Target/ARM/ARMLoadStoreOptimizer.cpp @@ -120,7 +120,7 @@ static int getLoadStoreMultipleOpcode(int Opcode) { case ARM::FSTD: NumFSTMGened++; return ARM::FSTMD; - default: llvm_report_error("Unhandled opcode!"); + default: LLVM_UNREACHABLE("Unhandled opcode!"); } return 0; } @@ -442,7 +442,7 @@ static unsigned getPreIndexedLoadStoreOpcode(unsigned Opc) { case ARM::FLDD: return ARM::FLDMD; case ARM::FSTS: return ARM::FSTMS; case ARM::FSTD: return ARM::FSTMD; - default: llvm_report_error("Unhandled opcode!"); + default: LLVM_UNREACHABLE("Unhandled opcode!"); } return 0; } @@ -455,7 +455,7 @@ static unsigned getPostIndexedLoadStoreOpcode(unsigned Opc) { case ARM::FLDD: return ARM::FLDMD; case ARM::FSTS: return ARM::FSTMS; case ARM::FSTD: return ARM::FSTMD; - default: llvm_report_error("Unhandled opcode!"); + default: LLVM_UNREACHABLE("Unhandled opcode!"); } return 0; } diff --git a/lib/Target/ARM/Thumb1RegisterInfo.cpp b/lib/Target/ARM/Thumb1RegisterInfo.cpp index 316f5ad22c..125b461253 100644 --- a/lib/Target/ARM/Thumb1RegisterInfo.cpp +++ b/lib/Target/ARM/Thumb1RegisterInfo.cpp @@ -32,6 +32,7 @@ #include "llvm/ADT/SmallVector.h" #include "llvm/Support/CommandLine.h" #include "llvm/Support/ErrorHandling.h" +#include "llvm/Support/raw_ostream.h" using namespace llvm; static cl::opt<bool> diff --git a/lib/Target/ARM/Thumb2RegisterInfo.cpp b/lib/Target/ARM/Thumb2RegisterInfo.cpp index bca205a039..f5a8b82478 100644 --- a/lib/Target/ARM/Thumb2RegisterInfo.cpp +++ b/lib/Target/ARM/Thumb2RegisterInfo.cpp @@ -455,8 +455,7 @@ void Thumb2RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, break; } default: - llvm_report_error("Unsupported addressing mode!"); - break; + LLVM_UNREACHABLE("Unsupported addressing mode!"); } Offset += InstrOffs * Scale; diff --git a/lib/Target/Alpha/AlphaCodeEmitter.cpp b/lib/Target/Alpha/AlphaCodeEmitter.cpp index 56f515e549..9a7c5a4f86 100644 --- a/lib/Target/Alpha/AlphaCodeEmitter.cpp +++ b/lib/Target/Alpha/AlphaCodeEmitter.cpp @@ -235,10 +235,10 @@ unsigned AlphaCodeEmitter::getMachineOpValue(const MachineInstr &MI, MCE.addRelocation(MachineRelocation::getBB(MCE.getCurrentPCOffset(), Alpha::reloc_bsr, MO.getMBB())); } else { - std::string msg; - raw_string_ostream Msg(msg); - Msg << "ERROR: Unknown type of MachineOperand: " << MO; - llvm_report_error(Msg.str()); +#ifndef NDEBUG + cerr << "ERROR: Unknown type of MachineOperand: " << MO << "\n"; +#endif + llvm_unreachable(); } return rv; diff --git a/lib/Target/Alpha/AlphaISelDAGToDAG.cpp b/lib/Target/Alpha/AlphaISelDAGToDAG.cpp index a774850461..6fa05fc108 100644 --- a/lib/Target/Alpha/AlphaISelDAGToDAG.cpp +++ b/lib/Target/Alpha/AlphaISelDAGToDAG.cpp @@ -28,7 +28,9 @@ #include "llvm/Intrinsics.h" #include "llvm/Support/Compiler.h" #include "llvm/Support/Debug.h" +#include "llvm/Support/ErrorHandling.h" #include "llvm/Support/MathExtras.h" +#include "llvm/Support/raw_ostream.h" #include <algorithm> using namespace llvm; diff --git a/lib/Target/Alpha/AlphaISelLowering.cpp b/lib/Target/Alpha/AlphaISelLowering.cpp index 176255c93d..49fb262b5a 100644 --- a/lib/Target/Alpha/AlphaISelLowering.cpp +++ b/lib/Target/Alpha/AlphaISelLowering.cpp @@ -25,6 +25,7 @@ #include "llvm/Intrinsics.h" #include "llvm/Support/CommandLine.h" #include "llvm/Support/ErrorHandling.h" +#include "llvm/Support/raw_ostream.h" using namespace llvm; /// AddLiveIn - This helper function adds the specified physical register to the diff --git a/lib/Target/Alpha/AlphaInstrInfo.cpp b/lib/Target/Alpha/AlphaInstrInfo.cpp index 17a9bc2f68..62b5d4c301 100644 --- a/lib/Target/Alpha/AlphaInstrInfo.cpp +++ b/lib/Target/Alpha/AlphaInstrInfo.cpp @@ -201,7 +201,7 @@ AlphaInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB, .addReg(SrcReg, getKillRegState(isKill)) .addFrameIndex(FrameIdx).addReg(Alpha::F31); else - llvm_report_error("Unhandled register class"); + LLVM_UNREACHABLE("Unhandled register class"); } void AlphaInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg, @@ -217,7 +217,7 @@ void AlphaInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg, else if (RC == Alpha::GPRCRegisterClass) Opc = Alpha::STQ; else - llvm_report_error("Unhandled register class"); + LLVM_UNREACHABLE("Unhandled register class"); DebugLoc DL = DebugLoc::getUnknownLoc(); MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc)).addReg(SrcReg, getKillRegState(isKill)); @@ -246,7 +246,7 @@ AlphaInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, BuildMI(MBB, MI, DL, get(Alpha::LDQ), DestReg) .addFrameIndex(FrameIdx).addReg(Alpha::F31); else - llvm_report_error("Unhandled register class"); + LLVM_UNREACHABLE("Unhandled register class"); } void AlphaInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg, @@ -261,7 +261,7 @@ void AlphaInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg, else if (RC == Alpha::GPRCRegisterClass) Opc = Alpha::LDQ; else - llvm_report_error("Unhandled register class"); + LLVM_UNREACHABLE("Unhandled register class"); DebugLoc DL = DebugLoc::getUnknownLoc(); MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg); diff --git a/lib/Target/Alpha/AlphaJITInfo.cpp b/lib/Target/Alpha/AlphaJITInfo.cpp index 6e9579a2a7..c62ab75523 100644 --- a/lib/Target/Alpha/AlphaJITInfo.cpp +++ b/lib/Target/Alpha/AlphaJITInfo.cpp @@ -18,6 +18,7 @@ #include "llvm/CodeGen/JITCodeEmitter.h" #include "llvm/Config/alloca.h" #include "llvm/Support/Debug.h" +#include "llvm/Support/ErrorHandling.h" #include <cstdlib> using namespace llvm; diff --git a/lib/Target/Alpha/AsmPrinter/AlphaAsmPrinter.cpp b/lib/Target/Alpha/AsmPrinter/AlphaAsmPrinter.cpp index feab490c64..11f177dd27 100644 --- a/lib/Target/Alpha/AsmPrinter/AlphaAsmPrinter.cpp +++ b/lib/Target/Alpha/AsmPrinter/AlphaAsmPrinter.cpp @@ -101,7 +101,7 @@ void AlphaAsmPrinter::printOp(const MachineOperand &MO, bool IsCallOp) { return; case MachineOperand::MO_Immediate: - llvm_report_error("printOp() does not handle immediate values"); + LLVM_UNREACHABLE("printOp() does not handle immediate values"); return; case MachineOperand::MO_MachineBasicBlock: diff --git a/lib/Target/CBackend/CBackend.cpp b/lib/Target/CBackend/CBackend.cpp index 294c6d35be..70495d0726 100644 --- a/lib/Target/CBackend/CBackend.cpp +++ b/lib/Target/CBackend/CBackend.cpp @@ -35,6 +35,7 @@ #include "llvm/Target/TargetData.h" #include "llvm/Support/CallSite.h" #include "llvm/Support/CFG.h" +#include "llvm/Support/ErrorHandling.h" #include "llvm/Support/GetElementPtrTypeIterator.h" #include "llvm/Support/InstVisitor.h" #include "llvm/Support/Mangler.h" @@ -321,8 +322,10 @@ namespace { void visitExtractValueInst(ExtractValueInst &I); void visitInstruction(Instruction &I) { +#ifndef NDEBUG cerr << "C Writer does not know about " << I; - abort(); +#endif + llvm_unreachable(); } void outputLValue(Instruction *I) { @@ -505,8 +508,10 @@ CWriter::printSimpleType(raw_ostream &Out, const Type *Ty, bool isSigned, } default: +#ifndef NDEBUG cerr << "Unknown primitive type: " << *Ty << "\n"; - abort(); +#endif + llvm_unreachable(); } } @@ -550,8 +555,10 @@ CWriter::printSimpleType(std::ostream &Out, const Type *Ty, bool isSigned, } default: +#ifndef NDEBUG cerr << "Unknown primitive type: " << *Ty << "\n"; - abort(); +#endif + llvm_unreachable(); } } @@ -652,8 +659,7 @@ raw_ostream &CWriter::printType(raw_ostream &Out, const Type *Ty, return Out << TyName << ' ' << NameSoFar; } default: - assert(0 && "Unhandled case in getTypeProps!"); - abort(); + LLVM_UNREACHABLE("Unhandled case in getTypeProps!"); } return Out; @@ -756,8 +762,7 @@ std::ostream &CWriter::printType(std::ostream &Out, const Type *Ty, return Out << TyName << ' ' << NameSoFar; } default: - assert(0 && "Unhandled case in getTypeProps!"); - abort(); + LLVM_UNREACHABLE("Unhandled case in getTypeProps!"); } return Out; @@ -1104,9 +1109,11 @@ void CWriter::printConstant(Constant *CPV, bool Static) { return; } default: +#ifndef NDEBUG cerr << "CWriter Error: Unhandled constant expression: " << *CE << "\n"; - abort(); +#endif + llvm_unreachable(); } } else if (isa<UndefValue>(CPV) && CPV->getType()->isSingleValueType()) { Out << "(("; @@ -1312,8 +1319,10 @@ void CWriter::printConstant(Constant *CPV, bool Static) { } // FALL THROUGH default: +#ifndef NDEBUG cerr << "Unknown constant type: " << *CPV << "\n"; - abort(); +#endif + llvm_unreachable(); } } @@ -1456,10 +1465,9 @@ void CWriter::writeInstComputationInline(Instruction &I) { const Type *Ty = I.getType(); if (Ty->isInteger() && (Ty!=Type::Int1Ty && Ty!=Type::Int8Ty && Ty!=Type::Int16Ty && Ty!=Type::Int32Ty && Ty!=Type::Int64Ty)) { - cerr << "The C backend does not currently support integer " - << "types of widths other than 1, 8, 16, 32, 64.\n"; - cerr << "This is being tracked as PR 4158.\n"; - abort(); + llvm_report_error("The C backend does not currently support integer " + "types of widths other than 1, 8, 16, 32, 64.\n" + "This is being tracked as PR 4158."); } // If this is a non-trivial bool computation, make sure to truncate down to @@ -2663,7 +2671,11 @@ void CWriter::visitBinaryOperator(Instruction &I) { case Instruction::Shl : Out << " << "; break; case Instruction::LShr: case Instruction::AShr: Out << " >> "; break; - default: cerr << "Invalid operator type!" << I; abort(); + default: +#ifndef NDEBUG + cerr << "Invalid operator type!" << I; +#endif + llvm_unreachable(); } writeOperandWithCast(I.getOperand(1), I.getOpcode()); @@ -2700,7 +2712,11 @@ void CWriter::visitICmpInst(ICmpInst &I) { case ICmpInst::ICMP_SLT: Out << " < "; break; case ICmpInst::ICMP_UGT: case ICmpInst::ICMP_SGT: Out << " > "; break; - default: cerr << "Invalid icmp predicate!" << I; abort(); + default: +#ifndef NDEBUG + cerr << "Invalid icmp predicate!" << I; +#endif + llvm_unreachable(); } writeOperandWithCast(I.getOperand(1), I); @@ -3020,10 +3036,12 @@ bool CWriter::visitBuiltinCall(CallInst &I, Intrinsic::ID ID, Out << ", "; // Output the last argument to the enclosing function. if (I.getParent()->getParent()->arg_empty()) { - cerr << "The C backend does not currently support zero " + std::string msg; + raw_string_ostream Msg(msg); + Msg << "The C backend does not currently support zero " << "argument varargs functions, such as '" - << I.getParent()->getParent()->getName() << "'!\n"; - abort(); + << I.getParent()->getParent()->getName() << "'!"; + llvm_report_error(Msg.str()); } writeOperand(--I.getParent()->getParent()->arg_end()); Out << ')'; diff --git a/lib/Target/CellSPU/AsmPrinter/SPUAsmPrinter.cpp b/lib/Target/CellSPU/AsmPrinter/SPUAsmPrinter.cpp index 2847d0b839..4d516438de 100644 --- a/lib/Target/CellSPU/AsmPrinter/SPUAsmPrinter.cpp +++ b/lib/Target/CellSPU/AsmPrinter/SPUAsmPrinter.cpp @@ -30,6 +30,7 @@ #include "llvm/Support/MathExtras.h" #include "llvm/Support/CommandLine.h" #include "llvm/Support/Debug.h" +#include "llvm/Support/ErrorHandling.h" #include "llvm/Support/Compiler.h" #include "llvm/Support/raw_ostream.h" #include "llvm/Target/TargetAsmInfo.h" @@ -319,8 +320,7 @@ namespace { void SPUAsmPrinter::printOp(const MachineOperand &MO) { switch (MO.getType()) { case MachineOperand::MO_Immediate: - cerr << "printOp() does not handle immediate values\n"; - abort(); + llvm_report_error("printOp() does not handle immediate values"); return; case MachineOperand::MO_MachineBasicBlock: @@ -573,8 +573,7 @@ void LinuxAsmPrinter::printModuleLevelGV(const GlobalVariable* GVar) { case GlobalValue::InternalLinkage: break; default: - cerr << "Unknown linkage type!"; - abort(); + llvm_report_error("Unknown linkage type!"); } EmitAlignment(Align, GVar); diff --git a/lib/Target/CellSPU/SPUISelDAGToDAG.cpp b/lib/Target/CellSPU/SPUISelDAGToDAG.cpp index 779d75d021..f9801d5349 100644 --- a/lib/Target/CellSPU/SPUISelDAGToDAG.cpp +++ b/lib/Target/CellSPU/SPUISelDAGToDAG.cpp @@ -31,8 +31,10 @@ #include "llvm/GlobalValue.h" #include "llvm/Intrinsics.h" #include "llvm/Support/Debug.h" +#include "llvm/Support/ErrorHandling.h" #include "llvm/Support/MathExtras.h" #include "llvm/Support/Compiler.h" +#include "llvm/Support/raw_ostream.h" using namespace llvm; @@ -191,10 +193,11 @@ namespace { #ifndef NDEBUG if (retval == 0) { - cerr << "SPUISelDAGToDAG.cpp: getValueTypeMapEntry returns NULL for " - << VT.getMVTString() - << "\n"; - abort(); + std::string msg; + raw_string_ostream Msg(msg); + Msg << "SPUISelDAGToDAG.cpp: getValueTypeMapEntry returns NULL for " + << VT.getMVTString(); + llvm_report_error(Msg.str()); } #endif @@ -437,16 +440,14 @@ SPUDAGToDAGISel::SelectAFormAddr(SDValue Op, SDValue N, SDValue &Base, case ISD::Constant: case ISD::ConstantPool: case ISD::GlobalAddress: - cerr << "SPU SelectAFormAddr: Constant/Pool/Global not lowered.\n"; - abort(); + llvm_report_error("SPU SelectAFormAddr: Constant/Pool/Global not lowered."); /*NOTREACHED*/ case ISD::TargetConstant: case ISD::TargetGlobalAddress: case ISD::TargetJumpTable: - cerr << "SPUSelectAFormAddr: Target Constant/Pool/Global not wrapped as " - << "A-form address.\n"; - abort(); + llvm_report_error("SPUSelectAFormAddr: Target Constant/Pool/Global " + "not wrapped as A-form address."); /*NOTREACHED*/ case SPUISD::AFormAddr: @@ -730,10 +731,8 @@ SPUDAGToDAGISel::Select(SDValue Op) { switch (Op0VT.getSimpleVT()) { default: - cerr << "CellSPU Select: Unhandled zero/any extend MVT\n"; - abort(); + llvm_report_error("CellSPU Select: Unhandled zero/any extend MVT"); /*NOTREACHED*/ - break; case MVT::i32: shufMask = CurDAG->getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, CurDAG->getConstant(0x80808080, MVT::i32), @@ -900,10 +899,11 @@ SPUDAGToDAGISel::Select(SDValue Op) { const valtype_map_s *vtm = getValueTypeMapEntry(VT); if (vtm->ldresult_ins == 0) { - cerr << "LDRESULT for unsupported type: " - << VT.getMVTString() - << "\n"; - abort(); + std::string msg; + raw_string_ostream Msg(msg); + Msg << "LDRESULT for unsupported type: " + << VT.getMVTString(); + llvm_report_error(Msg.str()); } Opc = vtm->ldresult_ins; @@ -1231,8 +1231,8 @@ SDNode *SPUDAGToDAGISel::SelectI64Constant(uint64_t Value64, MVT OpVT, return CurDAG->getTargetNode(SPU::ORi64_v2i64, dl, OpVT, SDValue(emitBuildVector(i64vec), 0)); } else { - cerr << "SPUDAGToDAGISel::SelectI64Constant: Unhandled i64vec condition\n"; - abort(); + llvm_report_error("SPUDAGToDAGISel::SelectI64Constant: Unhandled i64vec" + "condition"); } } diff --git a/lib/Target/CellSPU/SPUISelLowering.cpp b/lib/Target/CellSPU/SPUISelLowering.cpp index d8a77766bd..7879007319 100644 --- a/lib/Target/CellSPU/SPUISelLowering.cpp +++ b/lib/Target/C |