diff options
| -rw-r--r-- | lib/Target/ARM/ARMISelDAGToDAG.cpp | 1 | ||||
| -rw-r--r-- | lib/Target/ARM/ARMInstrNEON.td | 4 | ||||
| -rw-r--r-- | lib/Target/ARM/NEONPreAllocPass.cpp | 1 | ||||
| -rw-r--r-- | test/CodeGen/ARM/vld3.ll | 12 |
4 files changed, 18 insertions, 0 deletions
diff --git a/lib/Target/ARM/ARMISelDAGToDAG.cpp b/lib/Target/ARM/ARMISelDAGToDAG.cpp index 27b0ed20fd..c68c645c2c 100644 --- a/lib/Target/ARM/ARMISelDAGToDAG.cpp +++ b/lib/Target/ARM/ARMISelDAGToDAG.cpp @@ -1396,6 +1396,7 @@ SDNode *ARMDAGToDAGISel::Select(SDValue Op) { case MVT::v4i16: Opc = ARM::VLD3d16; break; case MVT::v2f32: case MVT::v2i32: Opc = ARM::VLD3d32; break; + case MVT::v1i64: Opc = ARM::VLD3d64; break; } SDValue Chain = N->getOperand(0); const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc, Chain }; diff --git a/lib/Target/ARM/ARMInstrNEON.td b/lib/Target/ARM/ARMInstrNEON.td index 11117cca3a..e7601b2346 100644 --- a/lib/Target/ARM/ARMInstrNEON.td +++ b/lib/Target/ARM/ARMInstrNEON.td @@ -215,6 +215,10 @@ class VLD3WB<bits<4> op7_4, string OpcodeStr> def VLD3d8 : VLD3D<0b0000, "vld3.8">; def VLD3d16 : VLD3D<0b0100, "vld3.16">; def VLD3d32 : VLD3D<0b1000, "vld3.32">; +def VLD3d64 : NLdSt<0,0b10,0b0110,0b1100, + (outs DPR:$dst1, DPR:$dst2, DPR:$dst3), + (ins addrmode6:$addr), IIC_VLD1, + "vld1.64\t\\{$dst1,$dst2,$dst3\\}, $addr", "", []>; // vld3 to double-spaced even registers. def VLD3q8a : VLD3WB<0b0000, "vld3.8">; diff --git a/lib/Target/ARM/NEONPreAllocPass.cpp b/lib/Target/ARM/NEONPreAllocPass.cpp index e795e1a755..52a43aaccf 100644 --- a/lib/Target/ARM/NEONPreAllocPass.cpp +++ b/lib/Target/ARM/NEONPreAllocPass.cpp @@ -67,6 +67,7 @@ static bool isNEONMultiRegOp(int Opcode, unsigned &FirstOpnd, unsigned &NumRegs, case ARM::VLD3d8: case ARM::VLD3d16: case ARM::VLD3d32: + case ARM::VLD3d64: case ARM::VLD3LNd8: case ARM::VLD3LNd16: case ARM::VLD3LNd32: diff --git a/test/CodeGen/ARM/vld3.ll b/test/CodeGen/ARM/vld3.ll index 4ed53092c3..207dc6a22e 100644 --- a/test/CodeGen/ARM/vld3.ll +++ b/test/CodeGen/ARM/vld3.ll @@ -4,6 +4,7 @@ %struct.__neon_int16x4x3_t = type { <4 x i16>, <4 x i16>, <4 x i16> } %struct.__neon_int32x2x3_t = type { <2 x i32>, <2 x i32>, <2 x i32> } %struct.__neon_float32x2x3_t = type { <2 x float>, <2 x float>, <2 x float> } +%struct.__neon_int64x1x3_t = type { <1 x i64>, <1 x i64>, <1 x i64> } %struct.__neon_int8x16x3_t = type { <16 x i8>, <16 x i8>, <16 x i8> } %struct.__neon_int16x8x3_t = type { <8 x i16>, <8 x i16>, <8 x i16> } @@ -50,6 +51,16 @@ define <2 x float> @vld3f(float* %A) nounwind { ret <2 x float> %tmp4 } +define <1 x i64> @vld3i64(i64* %A) nounwind { +;CHECK: vld3i64: +;CHECK: vld1.64 + %tmp1 = call %struct.__neon_int64x1x3_t @llvm.arm.neon.vld3.v1i64(i64* %A) + %tmp2 = extractvalue %struct.__neon_int64x1x3_t %tmp1, 0 + %tmp3 = extractvalue %struct.__neon_int64x1x3_t %tmp1, 2 + %tmp4 = add <1 x i64> %tmp2, %tmp3 + ret <1 x i64> %tmp4 +} + define <16 x i8> @vld3Qi8(i8* %A) nounwind { ;CHECK: vld3Qi8: ;CHECK: vld3.8 @@ -98,6 +109,7 @@ declare %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3.v8i8(i8*) nounwind readonl declare %struct.__neon_int16x4x3_t @llvm.arm.neon.vld3.v4i16(i8*) nounwind readonly declare %struct.__neon_int32x2x3_t @llvm.arm.neon.vld3.v2i32(i8*) nounwind readonly declare %struct.__neon_float32x2x3_t @llvm.arm.neon.vld3.v2f32(i8*) nounwind readonly +declare %struct.__neon_int64x1x3_t @llvm.arm.neon.vld3.v1i64(i8*) nounwind readonly declare %struct.__neon_int8x16x3_t @llvm.arm.neon.vld3.v16i8(i8*) nounwind readonly declare %struct.__neon_int16x8x3_t @llvm.arm.neon.vld3.v8i16(i8*) nounwind readonly |