diff options
| -rw-r--r-- | lib/Target/ARM/ARMExpandPseudoInsts.cpp | 29 | ||||
| -rw-r--r-- | lib/Target/ARM/ARMNaClRewritePass.cpp | 6 | ||||
| -rw-r--r-- | lib/Target/ARM/ARMSubtarget.h | 1 |
3 files changed, 11 insertions, 25 deletions
diff --git a/lib/Target/ARM/ARMExpandPseudoInsts.cpp b/lib/Target/ARM/ARMExpandPseudoInsts.cpp index 0fa3fe9bc8..def31450e2 100644 --- a/lib/Target/ARM/ARMExpandPseudoInsts.cpp +++ b/lib/Target/ARM/ARMExpandPseudoInsts.cpp @@ -935,31 +935,22 @@ bool ARMExpandPseudo::ExpandMI(MachineBasicBlock &MBB, if (!STI->isTargetNaCl() || llvm::TLSUseCall) { // Don't add implicit uses/defs for this call, otherwise // liveness analysis passes get confused. - MachineInstrBuilder MIB = - BuildMI_NoImp(MBB, MBBI, MI.getDebugLoc(), // @LOCALMOD - TII->get(Opcode == ARM::tTPsoft ? ARM::tBL : ARM::BL)) - .addExternalSymbol("__aeabi_read_tp", 0); - - MIB->setMemRefs(MI.memoperands_begin(), MI.memoperands_end()); + MachineInstrBuilder MIB = + BuildMI_NoImp(MBB, MBBI, MI.getDebugLoc(), // @LOCALMOD + TII->get(Opcode == ARM::tTPsoft ? ARM::tBL : ARM::BL)) + .addExternalSymbol("__aeabi_read_tp", 0); + MIB->setMemRefs(MI.memoperands_begin(), MI.memoperands_end()); TransferImpOps(MI, MIB, MIB); } else { // Inline version for native client. // See native_client/src/untrusted/nacl/aeabi_read_tp.S // .nexe builds use this version, while irt builds use a call to // __aeabi_read_tp. - if (FlagNaClUseM23ArmAbi) { - // mov r0, r9 - AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(), - TII->get(ARM::MOVr), ARM::R0) - .addReg(ARM::R9)) - .addReg(0); // Doesn't use/modify CPSR. - } else { - // ldr r0, [r9, #0] - AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(), - TII->get(ARM::LDRi12), ARM::R0) - .addReg(ARM::R9) - .addImm(0)); - } + // ldr r0, [r9, #0] + AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(), + TII->get(ARM::LDRi12), ARM::R0) + .addReg(ARM::R9) + .addImm(0)); } // @LOCALMOD-END MI.eraseFromParent(); diff --git a/lib/Target/ARM/ARMNaClRewritePass.cpp b/lib/Target/ARM/ARMNaClRewritePass.cpp index 505521cdc6..2644357320 100644 --- a/lib/Target/ARM/ARMNaClRewritePass.cpp +++ b/lib/Target/ARM/ARMNaClRewritePass.cpp @@ -53,10 +53,6 @@ FlagSfiStack("sfi-stack", cl::desc("enable sandboxing for stack changes")); cl::opt<bool> FlagSfiBranch("sfi-branch", cl::desc("enable sandboxing for branches")); -cl::opt<bool> -FlagNaClUseM23ArmAbi("nacl-use-m23-arm-abi", - cl::desc("use the Chrome M23 ARM ABI")); - } namespace { @@ -786,7 +782,7 @@ void ARMNaClRewritePass::SandboxMemory(MachineBasicBlock &MBB, bool IsLoad) { unsigned Addr = MI.getOperand(AddrIdx).getReg(); - if (!FlagNaClUseM23ArmAbi && Addr == ARM::R9) { + if (Addr == ARM::R9) { // R9-relative loads are no longer sandboxed. assert(IsLoad && "There should be no r9-relative stores"); } else { diff --git a/lib/Target/ARM/ARMSubtarget.h b/lib/Target/ARM/ARMSubtarget.h index bc32aece9a..112d3adfd4 100644 --- a/lib/Target/ARM/ARMSubtarget.h +++ b/lib/Target/ARM/ARMSubtarget.h @@ -27,7 +27,6 @@ #include "llvm/Support/CommandLine.h" namespace llvm { extern cl::opt<bool> FlagSfiDisableCP; - extern cl::opt<bool> FlagNaClUseM23ArmAbi; } // @LOCALMOD-END |