diff options
-rw-r--r-- | include/llvm/Bitcode/NaCl/NaClLLVMBitCodes.h | 5 | ||||
-rw-r--r-- | lib/Bitcode/NaCl/Reader/NaClBitcodeReader.cpp | 6 | ||||
-rw-r--r-- | lib/Bitcode/NaCl/Writer/NaClBitcodeWriter.cpp | 21 | ||||
-rw-r--r-- | lib/Bitcode/NaCl/Writer/NaClValueEnumerator.cpp | 5 | ||||
-rw-r--r-- | test/NaCl/Bitcode/bitcast-elide.ll | 34 | ||||
-rw-r--r-- | test/NaCl/Bitcode/inttoptr-elide.ll | 37 |
6 files changed, 94 insertions, 14 deletions
diff --git a/include/llvm/Bitcode/NaCl/NaClLLVMBitCodes.h b/include/llvm/Bitcode/NaCl/NaClLLVMBitCodes.h index 9b53e08ab8..b83bb0f95b 100644 --- a/include/llvm/Bitcode/NaCl/NaClLLVMBitCodes.h +++ b/include/llvm/Bitcode/NaCl/NaClLLVMBitCodes.h @@ -293,10 +293,7 @@ namespace naclbitc { // 21 is unused. // 22 is unused. FUNC_CODE_INST_VAARG = 23, // Not used in PNaCl. - // This store code encodes the pointer type, rather than the value type - // this is so information only available in the pointer type (e.g. address - // spaces) is retained. - FUNC_CODE_INST_STORE = 24, // STORE: [ptr, val, align, vol] + FUNC_CODE_INST_STORE = 24, // STORE: [ptr, val, align, vol] // 25 is unused. FUNC_CODE_INST_EXTRACTVAL = 26, // Not used in PNaCl. FUNC_CODE_INST_INSERTVAL = 27, // Not used in PNaCl. diff --git a/lib/Bitcode/NaCl/Reader/NaClBitcodeReader.cpp b/lib/Bitcode/NaCl/Reader/NaClBitcodeReader.cpp index ede06b2457..33ad03a246 100644 --- a/lib/Bitcode/NaCl/Reader/NaClBitcodeReader.cpp +++ b/lib/Bitcode/NaCl/Reader/NaClBitcodeReader.cpp @@ -1663,19 +1663,21 @@ bool NaClBitcodeReader::ParseFunctionBody(Function *F) { return Error("Invalid type for load instruction"); Op = ConvertOpToType(Op, T->getPointerTo(), CurBB); if (Op == 0) return true; + break; } } I = new LoadInst(Op, "", Record[OpNum+1], (1 << Record[OpNum]) >> 1); break; } - case naclbitc::FUNC_CODE_INST_STORE: { // STORE2:[ptr, val, align, vol] + case naclbitc::FUNC_CODE_INST_STORE: { // STORE: [ptr, val, align, vol] unsigned OpNum = 0; Value *Val, *Ptr; if (popValue(Record, &OpNum, NextValueNo, &Ptr) || popValue(Record, &OpNum, NextValueNo, &Val) || OpNum+2 != Record.size()) return Error("Invalid STORE record"); - + // Note: In version 1, the following statement is a noop. + Ptr = ConvertOpToType(Ptr, Val->getType()->getPointerTo(), CurBB); I = new StoreInst(Val, Ptr, Record[OpNum+1], (1 << Record[OpNum]) >> 1); break; } diff --git a/lib/Bitcode/NaCl/Writer/NaClBitcodeWriter.cpp b/lib/Bitcode/NaCl/Writer/NaClBitcodeWriter.cpp index ac2a6a0acf..9152879ff1 100644 --- a/lib/Bitcode/NaCl/Writer/NaClBitcodeWriter.cpp +++ b/lib/Bitcode/NaCl/Writer/NaClBitcodeWriter.cpp @@ -91,7 +91,8 @@ enum { FUNCTION_INST_RET_VAL_ABBREV, FUNCTION_INST_UNREACHABLE_ABBREV, FUNCTION_INST_FORWARDTYPEREF_ABBREV, - FUNCTION_INST_MAX_ABBREV = FUNCTION_INST_FORWARDTYPEREF_ABBREV, + FUNCTION_INST_STORE_ABBREV, + FUNCTION_INST_MAX_ABBREV = FUNCTION_INST_STORE_ABBREV, // TYPE_BLOCK_ID_NEW abbrev id's. TYPE_POINTER_ABBREV = naclbitc::FIRST_APPLICATION_ABBREV, @@ -1016,10 +1017,11 @@ static bool WriteInstruction(const Instruction &I, unsigned InstID, Vals.push_back(VE.getTypeID(I.getType())); } break; - case Instruction::Store: + case Instruction::Store: // STORE: [ptr, val, align, vol] Code = naclbitc::FUNC_CODE_INST_STORE; - pushValue(I.getOperand(1), InstID, Vals, VE, Stream); // ptrty + ptr - pushValue(I.getOperand(0), InstID, Vals, VE, Stream); // val. + AbbrevToUse = FUNCTION_INST_STORE_ABBREV; + pushValue(I.getOperand(1), InstID, Vals, VE, Stream); + pushValue(I.getOperand(0), InstID, Vals, VE, Stream); Vals.push_back(Log2_32(cast<StoreInst>(I).getAlignment())+1); Vals.push_back(cast<StoreInst>(I).isVolatile()); break; @@ -1315,6 +1317,17 @@ static void WriteBlockInfo(const NaClValueEnumerator &VE, Abbv) != FUNCTION_INST_FORWARDTYPEREF_ABBREV) llvm_unreachable("Unexpected abbrev ordering!"); } + { // INST_STORE abbrev for FUNCTION_BLOCK. + NaClBitCodeAbbrev *Abbv = new NaClBitCodeAbbrev(); + Abbv->Add(NaClBitCodeAbbrevOp(naclbitc::FUNC_CODE_INST_STORE)); + Abbv->Add(NaClBitCodeAbbrevOp(NaClBitCodeAbbrevOp::VBR, 6)); // Ptr + Abbv->Add(NaClBitCodeAbbrevOp(NaClBitCodeAbbrevOp::VBR, 6)); // Value + Abbv->Add(NaClBitCodeAbbrevOp(NaClBitCodeAbbrevOp::VBR, 4)); // Align + Abbv->Add(NaClBitCodeAbbrevOp(NaClBitCodeAbbrevOp::Fixed, 1)); // volatile + if (Stream.EmitBlockInfoAbbrev(naclbitc::FUNCTION_BLOCK_ID, + Abbv) != FUNCTION_INST_STORE_ABBREV) + llvm_unreachable("Unexpected abbrev ordering!"); + } { // VAR abbrev for GLOBALVAR_BLOCK. NaClBitCodeAbbrev *Abbv = new NaClBitCodeAbbrev(); diff --git a/lib/Bitcode/NaCl/Writer/NaClValueEnumerator.cpp b/lib/Bitcode/NaCl/Writer/NaClValueEnumerator.cpp index 11e1161bf8..34f4f2bbe9 100644 --- a/lib/Bitcode/NaCl/Writer/NaClValueEnumerator.cpp +++ b/lib/Bitcode/NaCl/Writer/NaClValueEnumerator.cpp @@ -443,7 +443,12 @@ static bool AllowsNormalizedPtr(const Value *V, const Instruction *Arg) { default: return false; case Instruction::Load: + // Verify it is the ptr argument of the load. Note: This check is + // not really necessary in that a load only has one argument. return I->getOperand(0) == Arg; + case Instruction::Store: + // Verify it is the ptr argument of the store. + return I->getOperand(1) == Arg; } } diff --git a/test/NaCl/Bitcode/bitcast-elide.ll b/test/NaCl/Bitcode/bitcast-elide.ll index 1c4e2e6e29..37c19fb94c 100644 --- a/test/NaCl/Bitcode/bitcast-elide.ll +++ b/test/NaCl/Bitcode/bitcast-elide.ll @@ -210,4 +210,36 @@ define i32 @TwoLoadOpt(i32 %i) { ; PF2-NEXT: <INST_LOAD abbrevid=4 op0=3 op1=3 op2=0 op3=0/> ; PF2-NEXT: <INST_BINOP abbrevid=5 op0=2 op1=1 op2=0/> ; PF2-NEXT: <INST_RET abbrevid=9 op0=1/> -; PF2: </FUNCTION_BLOCK> +; PF2: </FUNCTION_BLOCK> + +; Test that we elide the simple case of bitcast for a store. +define void @SimpleStore(i32 %i) { + %1 = bitcast [7 x i8]* @bytes to i32* + store i32 %i, i32* %1, align 4 + ret void +} + +; TD1: define void @SimpleStore(i32 %i) { +; TD1-NEXT: %1 = bitcast [7 x i8]* @bytes to i32* +; TD1-NEXT: store i32 %i, i32* %1, align 4 +; TD1-NEXT: ret void +; TD1-NEXT: } + +; PF1: <FUNCTION_BLOCK NumWords=6 BlockCodeSize=4> +; PF1-NEXT: <DECLAREBLOCKS op0=1/> +; PF1-NEXT: <INST_CAST abbrevid=7 op0=2 op1=1 op2=11/> +; PF1-NEXT: <INST_STORE abbrevid=12 op0=1 op1=2 op2=3 op3=0/> +; PF1-NEXT: <INST_RET abbrevid=8/> +; PF1: </FUNCTION_BLOCK> + +; TD2: define void @SimpleStore(i32 %i) { +; TD2-NEXT: %1 = bitcast [7 x i8]* @bytes to i32* +; TD2-NEXT: store i32 %i, i32* %1, align 4 +; TD2-NEXT: ret void +; TD2-NEXT: } + +; PF2: <FUNCTION_BLOCK NumWords=5 BlockCodeSize=4> +; PF2-NEXT: <DECLAREBLOCKS op0=1/> +; PF2-NEXT: <INST_STORE abbrevid=12 op0=2 op1=1 op2=3 op3=0/> +; PF2-NEXT: <INST_RET abbrevid=8/> +; PF2: </FUNCTION_BLOCK> diff --git a/test/NaCl/Bitcode/inttoptr-elide.ll b/test/NaCl/Bitcode/inttoptr-elide.ll index 2f35389fa5..988e16ea7b 100644 --- a/test/NaCl/Bitcode/inttoptr-elide.ll +++ b/test/NaCl/Bitcode/inttoptr-elide.ll @@ -174,7 +174,38 @@ define i32 @TwoLoadOpt(i32 %i) { ; PF2-NEXT: <INST_LOAD abbrevid=4 op0=2 op1=3 op2=0 op3=0/> ; PF2-NEXT: <INST_BINOP abbrevid=5 op0=2 op1=1 op2=0/> ; PF2-NEXT: <INST_RET abbrevid=9 op0=1/> -; PF2-NEXT: <VALUE_SYMTAB NumWords=1 BlockCodeSize=3> -; PF2-NEXT: <ENTRY abbrevid=6 op0=4 op1=105/> -; PF2-NEXT: </VALUE_SYMTAB> ; PF2: </FUNCTION_BLOCK> + +; ------------------------------------------------------ + +; Test that we elide the simple case of inttoptr for a store. +define void @SimpleStore(i32 %i) { + %1 = inttoptr i32 %i to i32* + store i32 %i, i32* %1, align 4 + ret void +} + +; TD1: define void @SimpleStore(i32 %i) { +; TD1-NEXT: %1 = inttoptr i32 %i to i32* +; TD1-NEXT: store i32 %i, i32* %1, align 4 +; TD1-NEXT: ret void +; TD1-NEXT: } + +; PF1: <FUNCTION_BLOCK NumWords=6 BlockCodeSize=4> +; PF1-NEXT: <DECLAREBLOCKS op0=1/> +; PF1-NEXT: <INST_CAST abbrevid=7 op0=1 op1=1 op2=10/> +; PF1-NEXT: <INST_STORE abbrevid=12 op0=1 op1=2 op2=3 op3=0/> +; PF1-NEXT: <INST_RET abbrevid=8/> +; PF1: </FUNCTION_BLOCK> + +; TD2: define void @SimpleStore(i32 %i) { +; TD2-NEXT: %1 = inttoptr i32 %i to i32* +; TD2-NEXT: store i32 %i, i32* %1, align 4 +; TD2-NEXT: ret void +; TD2-NEXT: } + +; PF2: <FUNCTION_BLOCK NumWords=5 BlockCodeSize=4> +; PF2-NEXT: <DECLAREBLOCKS op0=1/> +; PF2-NEXT: <INST_STORE abbrevid=12 op0=1 op1=1 op2=3 op3=0/> +; PF2-NEXT: <INST_RET abbrevid=8/> +; PF2T: </FUNCTION_BLOCK> |