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-rw-r--r--lib/Target/XCore/XCore.td7
-rw-r--r--lib/Target/XCore/XCoreISelDAGToDAG.cpp41
-rw-r--r--lib/Target/XCore/XCoreISelLowering.cpp52
-rw-r--r--lib/Target/XCore/XCoreInstrInfo.td17
-rw-r--r--lib/Target/XCore/XCoreSubtarget.cpp3
-rw-r--r--lib/Target/XCore/XCoreSubtarget.h2
-rw-r--r--lib/Target/XCore/XCoreTargetObjectFile.cpp21
7 files changed, 45 insertions, 98 deletions
diff --git a/lib/Target/XCore/XCore.td b/lib/Target/XCore/XCore.td
index 7a2dcdbf9f..5978a1596c 100644
--- a/lib/Target/XCore/XCore.td
+++ b/lib/Target/XCore/XCore.td
@@ -33,10 +33,6 @@ def XCoreInstrInfo : InstrInfo {
// XCore Subtarget features.
//===----------------------------------------------------------------------===//
-def FeatureXS1A
- : SubtargetFeature<"xs1a", "IsXS1A", "true",
- "Enable XS1A instructions">;
-
def FeatureXS1B
: SubtargetFeature<"xs1b", "IsXS1B", "true",
"Enable XS1B instructions">;
@@ -48,8 +44,7 @@ def FeatureXS1B
class Proc<string Name, list<SubtargetFeature> Features>
: Processor<Name, NoItineraries, Features>;
-def : Proc<"generic", [FeatureXS1A]>;
-def : Proc<"xs1a-generic", [FeatureXS1A]>;
+def : Proc<"generic", [FeatureXS1B]>;
def : Proc<"xs1b-generic", [FeatureXS1B]>;
//===----------------------------------------------------------------------===//
diff --git a/lib/Target/XCore/XCoreISelDAGToDAG.cpp b/lib/Target/XCore/XCoreISelDAGToDAG.cpp
index 258966cb9f..860b72f940 100644
--- a/lib/Target/XCore/XCoreISelDAGToDAG.cpp
+++ b/lib/Target/XCore/XCoreISelDAGToDAG.cpp
@@ -186,17 +186,14 @@ SDNode *XCoreDAGToDAGISel::Select(SDValue Op) {
}
case ISD::SMUL_LOHI: {
// FIXME fold addition into the macc instruction
- if (!Subtarget.isXS1A()) {
- SDValue Zero(CurDAG->getMachineNode(XCore::LDC_ru6, dl, MVT::i32,
- CurDAG->getTargetConstant(0, MVT::i32)), 0);
- SDValue Ops[] = { Zero, Zero, Op.getOperand(0), Op.getOperand(1) };
- SDNode *ResNode = CurDAG->getMachineNode(XCore::MACCS_l4r, dl,
- MVT::i32, MVT::i32, Ops, 4);
- ReplaceUses(SDValue(N, 0), SDValue(ResNode, 1));
- ReplaceUses(SDValue(N, 1), SDValue(ResNode, 0));
- return NULL;
- }
- break;
+ SDValue Zero(CurDAG->getMachineNode(XCore::LDC_ru6, dl, MVT::i32,
+ CurDAG->getTargetConstant(0, MVT::i32)), 0);
+ SDValue Ops[] = { Zero, Zero, Op.getOperand(0), Op.getOperand(1) };
+ SDNode *ResNode = CurDAG->getMachineNode(XCore::MACCS_l4r, dl,
+ MVT::i32, MVT::i32, Ops, 4);
+ ReplaceUses(SDValue(N, 0), SDValue(ResNode, 1));
+ ReplaceUses(SDValue(N, 1), SDValue(ResNode, 0));
+ return NULL;
}
case ISD::UMUL_LOHI: {
// FIXME fold addition into the macc / lmul instruction
@@ -211,22 +208,16 @@ SDNode *XCoreDAGToDAGISel::Select(SDValue Op) {
return NULL;
}
case XCoreISD::LADD: {
- if (!Subtarget.isXS1A()) {
- SDValue Ops[] = { Op.getOperand(0), Op.getOperand(1),
- Op.getOperand(2) };
- return CurDAG->getMachineNode(XCore::LADD_l5r, dl, MVT::i32, MVT::i32,
- Ops, 3);
- }
- break;
+ SDValue Ops[] = { Op.getOperand(0), Op.getOperand(1),
+ Op.getOperand(2) };
+ return CurDAG->getMachineNode(XCore::LADD_l5r, dl, MVT::i32, MVT::i32,
+ Ops, 3);
}
case XCoreISD::LSUB: {
- if (!Subtarget.isXS1A()) {
- SDValue Ops[] = { Op.getOperand(0), Op.getOperand(1),
- Op.getOperand(2) };
- return CurDAG->getMachineNode(XCore::LSUB_l5r, dl, MVT::i32, MVT::i32,
- Ops, 3);
- }
- break;
+ SDValue Ops[] = { Op.getOperand(0), Op.getOperand(1),
+ Op.getOperand(2) };
+ return CurDAG->getMachineNode(XCore::LSUB_l5r, dl, MVT::i32, MVT::i32,
+ Ops, 3);
}
// Other cases are autogenerated.
}
diff --git a/lib/Target/XCore/XCoreISelLowering.cpp b/lib/Target/XCore/XCoreISelLowering.cpp
index c99769448e..10d7730f55 100644
--- a/lib/Target/XCore/XCoreISelLowering.cpp
+++ b/lib/Target/XCore/XCoreISelLowering.cpp
@@ -89,13 +89,8 @@ XCoreTargetLowering::XCoreTargetLowering(XCoreTargetMachine &XTM)
setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
// 64bit
- if (!Subtarget.isXS1A()) {
- setOperationAction(ISD::ADD, MVT::i64, Custom);
- setOperationAction(ISD::SUB, MVT::i64, Custom);
- }
- if (Subtarget.isXS1A()) {
- setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
- }
+ setOperationAction(ISD::ADD, MVT::i64, Custom);
+ setOperationAction(ISD::SUB, MVT::i64, Custom);
setOperationAction(ISD::MULHS, MVT::i32, Expand);
setOperationAction(ISD::MULHU, MVT::i32, Expand);
setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
@@ -221,17 +216,16 @@ getGlobalAddressWrapper(SDValue GA, GlobalValue *GV, SelectionDAG &DAG)
DebugLoc dl = GA.getDebugLoc();
if (isa<Function>(GV)) {
return DAG.getNode(XCoreISD::PCRelativeWrapper, dl, MVT::i32, GA);
- } else if (!Subtarget.isXS1A()) {
- const GlobalVariable *GVar = dyn_cast<GlobalVariable>(GV);
- if (!GVar) {
- // If GV is an alias then use the aliasee to determine constness
- if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV))
- GVar = dyn_cast_or_null<GlobalVariable>(GA->resolveAliasedGlobal());
- }
- bool isConst = GVar && GVar->isConstant();
- if (isConst) {
- return DAG.getNode(XCoreISD::CPRelativeWrapper, dl, MVT::i32, GA);
- }
+ }
+ const GlobalVariable *GVar = dyn_cast<GlobalVariable>(GV);
+ if (!GVar) {
+ // If GV is an alias then use the aliasee to determine constness
+ if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV))
+ GVar = dyn_cast_or_null<GlobalVariable>(GA->resolveAliasedGlobal());
+ }
+ bool isConst = GVar && GVar->isConstant();
+ if (isConst) {
+ return DAG.getNode(XCoreISD::CPRelativeWrapper, dl, MVT::i32, GA);
}
return DAG.getNode(XCoreISD::DPRelativeWrapper, dl, MVT::i32, GA);
}
@@ -297,21 +291,16 @@ LowerConstantPool(SDValue Op, SelectionDAG &DAG)
ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
// FIXME there isn't really debug info here
DebugLoc dl = CP->getDebugLoc();
- if (Subtarget.isXS1A()) {
- llvm_unreachable("Lowering of constant pool unimplemented");
- return SDValue();
+ EVT PtrVT = Op.getValueType();
+ SDValue Res;
+ if (CP->isMachineConstantPoolEntry()) {
+ Res = DAG.getTargetConstantPool(CP->getMachineCPVal(), PtrVT,
+ CP->getAlignment());
} else {
- EVT PtrVT = Op.getValueType();
- SDValue Res;
- if (CP->isMachineConstantPoolEntry()) {
- Res = DAG.getTargetConstantPool(CP->getMachineCPVal(), PtrVT,
- CP->getAlignment());
- } else {
- Res = DAG.getTargetConstantPool(CP->getConstVal(), PtrVT,
- CP->getAlignment());
- }
- return DAG.getNode(XCoreISD::CPRelativeWrapper, dl, MVT::i32, Res);
+ Res = DAG.getTargetConstantPool(CP->getConstVal(), PtrVT,
+ CP->getAlignment());
}
+ return DAG.getNode(XCoreISD::CPRelativeWrapper, dl, MVT::i32, Res);
}
SDValue XCoreTargetLowering::
@@ -524,7 +513,6 @@ ExpandADDSUB(SDNode *N, SelectionDAG &DAG)
assert(N->getValueType(0) == MVT::i64 &&
(N->getOpcode() == ISD::ADD || N->getOpcode() == ISD::SUB) &&
"Unknown operand to lower!");
- assert(!Subtarget.isXS1A() && "Cannot custom lower ADD/SUB on xs1a");
DebugLoc dl = N->getDebugLoc();
// Extract components
diff --git a/lib/Target/XCore/XCoreInstrInfo.td b/lib/Target/XCore/XCoreInstrInfo.td
index 9d9cbf0e8e..c04ce93871 100644
--- a/lib/Target/XCore/XCoreInstrInfo.td
+++ b/lib/Target/XCore/XCoreInstrInfo.td
@@ -26,10 +26,6 @@ include "XCoreInstrFormats.td"
// Feature predicates.
//===----------------------------------------------------------------------===//
-// HasXS1A - This predicate is true when the target processor supports XS1A
-// instructions.
-def HasXS1A : Predicate<"Subtarget.isXS1A()">;
-
// HasXS1B - This predicate is true when the target processor supports XS1B
// instructions.
def HasXS1B : Predicate<"Subtarget.isXS1B()">;
@@ -142,9 +138,6 @@ def immU20 : PatLeaf<(imm), [{
return (uint32_t)N->getZExtValue() < (1 << 20);
}]>;
-// FIXME check subtarget. Currently we check if the immediate
-// is in the common subset of legal immediate values for both
-// XS1A and XS1B.
def immMskBitp : PatLeaf<(imm), [{
uint32_t value = (uint32_t)N->getZExtValue();
if (!isMask_32(value)) {
@@ -157,9 +150,6 @@ def immMskBitp : PatLeaf<(imm), [{
|| msksize == 32;
}]>;
-// FIXME check subtarget. Currently we check if the immediate
-// is in the common subset of legal immediate values for both
-// XS1A and XS1B.
def immBitp : PatLeaf<(imm), [{
uint32_t value = (uint32_t)N->getZExtValue();
return (value >= 1 && value <= 8)
@@ -524,13 +514,6 @@ def LMUL_l6r : _L6R<(outs GRRegs:$dst1, GRRegs:$dst2),
"lmul $dst1, $dst2, $src1, $src2, $src3, $src4",
[]>;
-let Predicates = [HasXS1A] in
-def MACC_l6r : _L6R<(outs GRRegs:$dst1, GRRegs:$dst2),
- (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3,
- GRRegs:$src4),
- "macc $dst1, $dst2, $src1, $src2, $src3, $src4",
- []>;
-
// Register - U6
//let Uses = [DP] in ...
diff --git a/lib/Target/XCore/XCoreSubtarget.cpp b/lib/Target/XCore/XCoreSubtarget.cpp
index 3dd712f834..2b2f9f1791 100644
--- a/lib/Target/XCore/XCoreSubtarget.cpp
+++ b/lib/Target/XCore/XCoreSubtarget.cpp
@@ -17,8 +17,7 @@
using namespace llvm;
XCoreSubtarget::XCoreSubtarget(const std::string &TT, const std::string &FS)
- : IsXS1A(false),
- IsXS1B(false)
+ : IsXS1B(false)
{
std::string CPU = "xs1b-generic";
diff --git a/lib/Target/XCore/XCoreSubtarget.h b/lib/Target/XCore/XCoreSubtarget.h
index 4839351487..34d142561c 100644
--- a/lib/Target/XCore/XCoreSubtarget.h
+++ b/lib/Target/XCore/XCoreSubtarget.h
@@ -22,7 +22,6 @@
namespace llvm {
class XCoreSubtarget : public TargetSubtarget {
- bool IsXS1A;
bool IsXS1B;
public:
@@ -31,7 +30,6 @@ public:
///
XCoreSubtarget(const std::string &TT, const std::string &FS);
- bool isXS1A() const { return IsXS1A; }
bool isXS1B() const { return IsXS1B; }
/// ParseSubtargetFeatures - Parses features string setting specified
diff --git a/lib/Target/XCore/XCoreTargetObjectFile.cpp b/lib/Target/XCore/XCoreTargetObjectFile.cpp
index c1990d6d0f..7de3b55d38 100644
--- a/lib/Target/XCore/XCoreTargetObjectFile.cpp
+++ b/lib/Target/XCore/XCoreTargetObjectFile.cpp
@@ -52,20 +52,13 @@ void XCoreTargetObjectFile::Initialize(MCContext &Ctx, const TargetMachine &TM){
// and can be placed in the standard data / bss sections.
TLSDataSection = DataSection;
TLSBSSSection = BSSSection;
-
- if (TM.getSubtarget<XCoreSubtarget>().isXS1A())
- ReadOnlySection = // FIXME: Why is this a writable section for XS1A?
- MCSectionXCore::Create(".dp.rodata", MCSectionELF::SHT_PROGBITS,
- MCSectionELF::SHF_ALLOC | MCSectionELF::SHF_WRITE |
- MCSectionXCore::SHF_DP_SECTION,
- SectionKind::getDataRel(), false, getContext());
- else
- ReadOnlySection =
- MCSectionXCore::Create(".cp.rodata", MCSectionELF::SHT_PROGBITS,
- MCSectionELF::SHF_ALLOC |
- MCSectionXCore::SHF_CP_SECTION,
- SectionKind::getReadOnlyWithRel(), false,
- getContext());
+
+ ReadOnlySection =
+ MCSectionXCore::Create(".cp.rodata", MCSectionELF::SHT_PROGBITS,
+ MCSectionELF::SHF_ALLOC |
+ MCSectionXCore::SHF_CP_SECTION,
+ SectionKind::getReadOnlyWithRel(), false,
+ getContext());
// Dynamic linking is not supported. Data with relocations is placed in the
// same section as data without relocations.
generated by cgit v1.2.3-18-g5258 (git 2.32.0) at 2024-11-24 20:24:15 +0000