diff options
| -rw-r--r-- | lib/Target/ARM/ARMInstrVFP.td | 8 | ||||
| -rw-r--r-- | lib/Target/ARM/Disassembler/ARMDisassembler.cpp | 8 | ||||
| -rw-r--r-- | test/MC/ARM/simple-fp-encoding.s | 21 |
3 files changed, 29 insertions, 8 deletions
diff --git a/lib/Target/ARM/ARMInstrVFP.td b/lib/Target/ARM/ARMInstrVFP.td index 4e2cda433b..23c132e4f6 100644 --- a/lib/Target/ARM/ARMInstrVFP.td +++ b/lib/Target/ARM/ARMInstrVFP.td @@ -567,8 +567,8 @@ def VMOVRRS : AVConv3I<0b11000101, 0b1010, bits<4> Rt2; // Encode instruction operands. - let Inst{3-0} = src1{3-0}; - let Inst{5} = src1{4}; + let Inst{3-0} = src1{4-1}; + let Inst{5} = src1{0}; let Inst{15-12} = Rt; let Inst{19-16} = Rt2; @@ -617,8 +617,8 @@ def VMOVSRR : AVConv5I<0b11000100, 0b1010, bits<4> src2; // Encode instruction operands. - let Inst{3-0} = dst1{3-0}; - let Inst{5} = dst1{4}; + let Inst{3-0} = dst1{4-1}; + let Inst{5} = dst1{0}; let Inst{15-12} = src1; let Inst{19-16} = src2; diff --git a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp index 66ea1171ff..8164e90d0a 100644 --- a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp +++ b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp @@ -4198,9 +4198,9 @@ static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn, DecodeStatus S = MCDisassembler::Success; unsigned Rt = fieldFromInstruction32(Insn, 12, 4); unsigned Rt2 = fieldFromInstruction32(Insn, 16, 4); - unsigned Rm = fieldFromInstruction32(Insn, 0, 4); + unsigned Rm = fieldFromInstruction32(Insn, 5, 1); unsigned pred = fieldFromInstruction32(Insn, 28, 4); - Rm |= fieldFromInstruction32(Insn, 5, 1) << 4; + Rm |= fieldFromInstruction32(Insn, 0, 4) << 4; if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) S = MCDisassembler::SoftFail; @@ -4224,9 +4224,9 @@ static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn, DecodeStatus S = MCDisassembler::Success; unsigned Rt = fieldFromInstruction32(Insn, 12, 4); unsigned Rt2 = fieldFromInstruction32(Insn, 16, 4); - unsigned Rm = fieldFromInstruction32(Insn, 0, 4); + unsigned Rm = fieldFromInstruction32(Insn, 5, 1); unsigned pred = fieldFromInstruction32(Insn, 28, 4); - Rm |= fieldFromInstruction32(Insn, 5, 1) << 4; + Rm |= fieldFromInstruction32(Insn, 0, 4) << 4; if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) S = MCDisassembler::SoftFail; diff --git a/test/MC/ARM/simple-fp-encoding.s b/test/MC/ARM/simple-fp-encoding.s index a766b9539a..2a226205a0 100644 --- a/test/MC/ARM/simple-fp-encoding.s +++ b/test/MC/ARM/simple-fp-encoding.s @@ -196,6 +196,27 @@ @ CHECK: vmov r0, r1, d16 @ encoding: [0x30,0x0b,0x51,0xec] vmov r0, r1, d16 +@ Between two single precision registers and two core registers + vmov s3, s4, r1, r2 + vmov s2, s3, r1, r2 + vmov r1, r2, s3, s4 + vmov r1, r2, s2, s3 +@ CHECK: vmov s3, s4, r1, r2 @ encoding: [0x31,0x1a,0x42,0xec] +@ CHECK: vmov s2, s3, r1, r2 @ encoding: [0x11,0x1a,0x42,0xec] +@ CHECK: vmov r1, r2, s3, s4 @ encoding: [0x31,0x1a,0x52,0xec] +@ CHECK: vmov r1, r2, s2, s3 @ encoding: [0x11,0x1a,0x52,0xec] + +@ Between one double precision register and two core registers + vmov d15, r1, r2 + vmov d16, r1, r2 + vmov r1, r2, d15 + vmov r1, r2, d16 +@ CHECK: vmov d15, r1, r2 @ encoding: [0x1f,0x1b,0x42,0xec] +@ CHECK: vmov d16, r1, r2 @ encoding: [0x30,0x1b,0x42,0xec] +@ CHECK: vmov r1, r2, d15 @ encoding: [0x1f,0x1b,0x52,0xec] +@ CHECK: vmov r1, r2, d16 @ encoding: [0x30,0x1b,0x52,0xec] + + @ CHECK: vldr d17, [r0] @ encoding: [0x00,0x1b,0xd0,0xed] @ CHECK: vldr s0, [lr] @ encoding: [0x00,0x0a,0x9e,0xed] @ CHECK: vldr d0, [lr] @ encoding: [0x00,0x0b,0x9e,0xed] |