diff options
| -rw-r--r-- | include/llvm/Target/TargetLowering.h | 5 | ||||
| -rw-r--r-- | lib/Target/Mips/MipsISelLowering.cpp | 11 | ||||
| -rw-r--r-- | lib/Target/Mips/MipsISelLowering.h | 1 | ||||
| -rw-r--r-- | lib/Transforms/NaCl/ResolvePNaClIntrinsics.cpp | 12 |
4 files changed, 24 insertions, 5 deletions
diff --git a/include/llvm/Target/TargetLowering.h b/include/llvm/Target/TargetLowering.h index 7ce6584762..091368382e 100644 --- a/include/llvm/Target/TargetLowering.h +++ b/include/llvm/Target/TargetLowering.h @@ -117,13 +117,14 @@ public: // @LOCALMOD-START // This needs to be kept in sync with - // native_client/src/untrusted/nacl/pnaclintrin.h. + // native_client/src/untrusted/nacl/pnacl.h. enum PnaclTargetArchitecture { PnaclTargetArchitectureInvalid = 0, PnaclTargetArchitectureX86_32, PnaclTargetArchitectureX86_64, PnaclTargetArchitectureARM_32, - PnaclTargetArchitectureARM_32_Thumb + PnaclTargetArchitectureARM_32_Thumb, + PnaclTargetArchitectureMips_32 }; // @LOCALMOD-END diff --git a/lib/Target/Mips/MipsISelLowering.cpp b/lib/Target/Mips/MipsISelLowering.cpp index f065400dfb..69f060965c 100644 --- a/lib/Target/Mips/MipsISelLowering.cpp +++ b/lib/Target/Mips/MipsISelLowering.cpp @@ -394,6 +394,7 @@ MipsTargetLowering(MipsTargetMachine &TM) if (Subtarget->isTargetNaCl()) { setOperationAction(ISD::NACL_TP_TLS_OFFSET, MVT::i32, Custom); setOperationAction(ISD::NACL_TP_TDB_OFFSET, MVT::i32, Custom); + setOperationAction(ISD::NACL_TARGET_ARCH, MVT::i32, Custom); } // @LOCALMOD-END @@ -762,6 +763,7 @@ LowerOperation(SDValue Op, SelectionDAG &DAG) const // @LOCALMOD-BEGIN case ISD::NACL_TP_TLS_OFFSET: return LowerNaClTpTlsOffset(Op, DAG); case ISD::NACL_TP_TDB_OFFSET: return LowerNaClTpTdbOffset(Op, DAG); + case ISD::NACL_TARGET_ARCH: return LowerNaClTargetArch(Op, DAG); // @LOCALMOD-END } return SDValue(); @@ -1516,6 +1518,15 @@ SDValue MipsTargetLowering::LowerNaClTpTdbOffset(SDValue Op, Op.getOperand(0)); } +SDValue +MipsTargetLowering::LowerNaClTargetArch(SDValue Op, SelectionDAG &DAG) const { + // size_t __nacl_target_arch () { + // return PnaclTargetArchitectureMips_32; + // } + return DAG.getConstant(PnaclTargetArchitectureMips_32, + Op.getValueType().getSimpleVT()); +} + SDValue MipsTargetLowering:: GetNaClThreadPointer(SelectionDAG &DAG, DebugLoc DL) const { EVT PtrVT = getPointerTy(); diff --git a/lib/Target/Mips/MipsISelLowering.h b/lib/Target/Mips/MipsISelLowering.h index 090f97ede3..de6ea56180 100644 --- a/lib/Target/Mips/MipsISelLowering.h +++ b/lib/Target/Mips/MipsISelLowering.h @@ -392,6 +392,7 @@ namespace llvm { // @LOCALMOD-BEGIN SDValue LowerNaClTpTlsOffset(SDValue Op, SelectionDAG &DAG) const; SDValue LowerNaClTpTdbOffset(SDValue Op, SelectionDAG &DAG) const; + SDValue LowerNaClTargetArch(SDValue Op, SelectionDAG &DAG) const; // @LOCALMOD-END virtual SDValue diff --git a/lib/Transforms/NaCl/ResolvePNaClIntrinsics.cpp b/lib/Transforms/NaCl/ResolvePNaClIntrinsics.cpp index 3550cd9aca..428caef2b5 100644 --- a/lib/Transforms/NaCl/ResolvePNaClIntrinsics.cpp +++ b/lib/Transforms/NaCl/ResolvePNaClIntrinsics.cpp @@ -160,13 +160,14 @@ private: /// Resolve __nacl_atomic_is_lock_free to true/false at translation /// time. PNaCl's currently supported platforms all support lock-free -/// atomics at byte sizes {1,2,4,8}, and the alignment of the pointer is -/// always expected to be natural (as guaranteed by C11 and +/// atomics at byte sizes {1,2,4,8} except for MIPS arch that supports +/// lock-free atomics at byte sizes {1,2,4}, and the alignment of the +/// pointer is always expected to be natural (as guaranteed by C11 and /// C++11). PNaCl's Module-level ABI verification checks that the byte /// size is constant and in {1,2,4,8}. struct IsLockFreeToConstant { Constant *operator()(CallInst *Call) { - const uint64_t MaxLockFreeByteSize = 8; + uint64_t MaxLockFreeByteSize = 8; const APInt &ByteSize = cast<Constant>(Call->getOperand(0))->getUniqueInteger(); @@ -176,11 +177,16 @@ struct IsLockFreeToConstant { case PnaclTargetArchitectureX86_64: case PnaclTargetArchitectureARM_32: break; + case PnaclTargetArchitectureMips_32: + MaxLockFreeByteSize = 4; + break; default: return false; } # elif defined(__i386__) || defined(__x86_64__) || defined(__arm__) // Continue. +# elif defined(__mips__) + MaxLockFreeByteSize = 4; # else # error "Unknown architecture" # endif |