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authorEli Friedman <eli.friedman@gmail.com>2011-07-16 02:41:28 +0000
committerEli Friedman <eli.friedman@gmail.com>2011-07-16 02:41:28 +0000
commit7105259ce8e9fd78ce9fc1b7a9aaab123fb5db64 (patch)
tree0b633db8bd7f42bebb93c34f0b2ca0ebcf08b630 /utils/TableGen/X86RecognizableInstr.h
parent5614769d557600fda3cf73b481581fe32fbff258 (diff)
Make the disassembler able to disassemble a bunch of instructions with names in the TableGen files containing "64" on x86-32. This includes a bunch of x87 instructions, like fld, and a bunch of SSSE3 instructions on MMX registers like pshufb. Part of PR8873.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135337 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'utils/TableGen/X86RecognizableInstr.h')
-rw-r--r--utils/TableGen/X86RecognizableInstr.h2
1 files changed, 2 insertions, 0 deletions
diff --git a/utils/TableGen/X86RecognizableInstr.h b/utils/TableGen/X86RecognizableInstr.h
index c7ec18ca6d..677d9f0155 100644
--- a/utils/TableGen/X86RecognizableInstr.h
+++ b/utils/TableGen/X86RecognizableInstr.h
@@ -64,6 +64,8 @@ private:
bool HasLockPrefix;
/// The isCodeGenOnly filed from the record
bool IsCodeGenOnly;
+ // Whether the instruction has the predicate "Mode64Bit"
+ bool Is64Bit;
/// The instruction name as listed in the tables
std::string Name;