Change instruction description to split OperandList into OutOperandList and

InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr  : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
                 "add{l} {$src2, $dst|$dst, $src2}",
                 [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr  : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
                 "add{l} {$src2, $dst|$dst, $src2}",
                 [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40033 91177308-0d34-0410-b5e6-96231b3b80d8

1 files changed, 12 insertions, 2 deletions

diff --git a/utils/TableGen/Record.cpp b/utils/TableGen/Record.cpp
index e81a361eae..75583bb1d1 100644
--- a/utils/TableGen/Record.cpp
+++ b/utils/TableGen/Record.cpp
@@ -396,8 +396,18 @@ Init *BinOpInit::Fold() {
     if (LHSs && RHSs) {
       DefInit *LOp = dynamic_cast<DefInit*>(LHSs->getOperator());
       DefInit *ROp = dynamic_cast<DefInit*>(RHSs->getOperator());
-      if (LOp->getDef() != ROp->getDef())
-        throw "Concated Dag operators do not match!";
+      if (LOp->getDef() != ROp->getDef()) {
+        bool LIsOps =
+          LOp->getDef()->getName() == "outs" ||
+          LOp->getDef()->getName() != "ins" ||
+          LOp->getDef()->getName() != "defs";
+        bool RIsOps =
+          ROp->getDef()->getName() == "outs" ||
+          ROp->getDef()->getName() != "ins" ||
+          ROp->getDef()->getName() != "defs";
+        if (!LIsOps || !RIsOps)
+          throw "Concated Dag operators do not match!";
+      }
       std::vector<Init*> Args;
       std::vector<std::string> ArgNames;
       for (unsigned i = 0, e = LHSs->getNumArgs(); i != e; ++i) {