diff options
author | Chris Lattner <sabre@nondot.org> | 2010-12-19 19:37:52 +0000 |
---|---|---|
committer | Chris Lattner <sabre@nondot.org> | 2010-12-19 19:37:52 +0000 |
commit | e5cbdca3bd4bc40ca31282531a9292f70648d265 (patch) | |
tree | e3ce4ae2434bb2160c3cb96db2c3379b46cbd85c /test/Transforms/InstCombine/overflow.ll | |
parent | 26b482d7a76df3f67675ce852daed0eba709c63e (diff) |
recognize an unsigned add with overflow idiom into uadd.
This resolves a README entry and technically resolves PR4916,
but we still get poor code for the testcase in that PR because
GVN isn't CSE'ing uadd with add, filed as PR8817.
Previously we got:
_test7: ## @test7
addq %rsi, %rdi
cmpq %rdi, %rsi
movl $42, %eax
cmovaq %rsi, %rax
ret
Now we get:
_test7: ## @test7
addq %rsi, %rdi
movl $42, %eax
cmovbq %rsi, %rax
ret
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122182 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/Transforms/InstCombine/overflow.ll')
-rw-r--r-- | test/Transforms/InstCombine/overflow.ll | 34 |
1 files changed, 34 insertions, 0 deletions
diff --git a/test/Transforms/InstCombine/overflow.ll b/test/Transforms/InstCombine/overflow.ll index 6a53d27749..9123283988 100644 --- a/test/Transforms/InstCombine/overflow.ll +++ b/test/Transforms/InstCombine/overflow.ll @@ -97,3 +97,37 @@ if.end: ; preds = %entry ; CHECK: ret i8 } +; CHECK: @test5 +; CHECK: llvm.uadd.with.overflow +; CHECK: ret i64 +define i64 @test5(i64 %a, i64 %b) nounwind ssp { +entry: + %add = add i64 %b, %a + %cmp = icmp ult i64 %add, %a + %Q = select i1 %cmp, i64 %b, i64 42 + ret i64 %Q +} + +; CHECK: @test6 +; CHECK: llvm.uadd.with.overflow +; CHECK: ret i64 +define i64 @test6(i64 %a, i64 %b) nounwind ssp { +entry: + %add = add i64 %b, %a + %cmp = icmp ult i64 %add, %b + %Q = select i1 %cmp, i64 %b, i64 42 + ret i64 %Q +} + +; CHECK: @test7 +; CHECK: llvm.uadd.with.overflow +; CHECK: ret i64 +define i64 @test7(i64 %a, i64 %b) nounwind ssp { +entry: + %add = add i64 %b, %a + %cmp = icmp ugt i64 %b, %add + %Q = select i1 %cmp, i64 %b, i64 42 + ret i64 %Q +} + + |