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| author | Craig Topper <craig.topper@gmail.com> | 2011-09-23 06:57:25 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@gmail.com> | 2011-09-23 06:57:25 +0000 |
| commit | 4da632e6e09b96db4b3f9202cde4e6ca732001c1 (patch) | |
| tree | 2b2c73074cefca6d6e072e2615db00e10753fd93 /test/MC | |
| parent | aaa9fc2e375ac92c9ff0cff5265c79045affe8ba (diff) | |
Don't allow 32-bit only instructions to be disassembled in 64-bit mode. Fixes part of PR10700.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140370 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/MC')
| -rw-r--r-- | test/MC/Disassembler/X86/intel-syntax.txt | 11 |
1 files changed, 4 insertions, 7 deletions
diff --git a/test/MC/Disassembler/X86/intel-syntax.txt b/test/MC/Disassembler/X86/intel-syntax.txt index b848418a52..c04dcd099b 100644 --- a/test/MC/Disassembler/X86/intel-syntax.txt +++ b/test/MC/Disassembler/X86/intel-syntax.txt @@ -12,14 +12,11 @@ # CHECK: movsq 0x48 0xa5 -# CHECK: pop DS -0x1f +# CHECK: pop FS +0x0f 0xa1 -# CHECK: pop ES -0x07 - -# CHECK: pop SS -0x17 +# CHECK: pop GS +0x0f 0xa9 # CHECK: in AL, DX 0xec |