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authorChris Lattner <sabre@nondot.org>2010-12-22 08:02:57 +0000
committerChris Lattner <sabre@nondot.org>2010-12-22 08:02:57 +0000
commitcbf68dfbc0b36de8ef20bb42ce0c7d75cb132fc7 (patch)
tree6eae5a8ce6203fee8812ca0e51d508d1e07a7823 /test/CodeGen
parent7a2a7faf9cfdbdf5f1de720385dc8a0009cd60a6 (diff)
Fix a bug in ReduceLoadWidth that wasn't handling extending
loads properly. We miscompiled the testcase into: _test: ## @test movl $128, (%rdi) movzbl 1(%rdi), %eax ret Now we get a proper: _test: ## @test movl $128, (%rdi) movsbl (%rdi), %eax movzbl %ah, %eax ret This fixes PR8757. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122392 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen')
-rw-r--r--test/CodeGen/X86/narrow-shl-load.ll24
1 files changed, 21 insertions, 3 deletions
diff --git a/test/CodeGen/X86/narrow-shl-load.ll b/test/CodeGen/X86/narrow-shl-load.ll
index 53b03884a5..ef27cbc341 100644
--- a/test/CodeGen/X86/narrow-shl-load.ll
+++ b/test/CodeGen/X86/narrow-shl-load.ll
@@ -6,7 +6,7 @@ target triple = "x86_64-pc-linux-gnu"
; DAGCombiner should fold this code in finite time.
; rdar://8606584
-define void @D() nounwind readnone {
+define void @test1() nounwind readnone {
bb.nph:
br label %while.cond
@@ -33,10 +33,10 @@ while.end: ; preds = %while.cond
; DAGCombiner shouldn't fold the sdiv (ashr) away.
; rdar://8636812
-; CHECK: main:
+; CHECK: test2:
; CHECK: sarl
-define i32 @main() nounwind {
+define i32 @test2() nounwind {
entry:
%i = alloca i32, align 4
%j = alloca i8, align 1
@@ -63,3 +63,21 @@ if.end: ; preds = %entry
declare void @abort() noreturn
declare void @exit(i32) noreturn
+
+; DAG Combiner can't fold this into a load of the 1'th byte.
+; PR8757
+define i32 @test3(i32 *%P) nounwind ssp {
+ volatile store i32 128, i32* %P
+ %tmp4.pre = load i32* %P
+ %phitmp = trunc i32 %tmp4.pre to i16
+ %phitmp13 = shl i16 %phitmp, 8
+ %phitmp14 = ashr i16 %phitmp13, 8
+ %phitmp15 = lshr i16 %phitmp14, 8
+ %phitmp16 = zext i16 %phitmp15 to i32
+ ret i32 %phitmp16
+
+; CHECK: movl $128, (%rdi)
+; CHECK-NEXT: movsbl (%rdi), %eax
+; CHECK-NEXT: movzbl %ah, %eax
+; CHECK-NEXT: ret
+}