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| author | Scott Michel <scottm@aero.org> | 2008-02-23 18:41:37 +0000 |
|---|---|---|
| committer | Scott Michel <scottm@aero.org> | 2008-02-23 18:41:37 +0000 |
| commit | a59d469e9b31087f0f045bcb5d1a154c963be9b7 (patch) | |
| tree | 69a653dae42a34dea6cb63148ac5c417ea1c3a65 /test/CodeGen | |
| parent | f65a0f7860bc9189c95a76cb6802d7ba54e61048 (diff) | |
Merge current work back to tree to minimize diffs and drift. Major highlights
for CellSPU modifications:
- SPUInstrInfo.td refactoring: "multiclass" really is _your_ friend.
- Other improvements based on refactoring effort in SPUISelLowering.cpp,
esp. in SPUISelLowering::PerformDAGCombine(), where zero amount shifts and
rotates are now eliminiated, other scalar-to-vector-to-scalar silliness
is also eliminated.
- 64-bit operations are being implemented, _muldi3.c gcc runtime now
compiles and generates the right code. More work still needs to be done.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47532 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen')
| -rw-r--r-- | test/CodeGen/CellSPU/mul_ops.ll | 5 |
1 files changed, 2 insertions, 3 deletions
diff --git a/test/CodeGen/CellSPU/mul_ops.ll b/test/CodeGen/CellSPU/mul_ops.ll index e1509d27cb..a67c572a7c 100644 --- a/test/CodeGen/CellSPU/mul_ops.ll +++ b/test/CodeGen/CellSPU/mul_ops.ll @@ -8,11 +8,10 @@ ; RUN: grep and %t1.s | count 2 ; RUN: grep selb %t1.s | count 6 ; RUN: grep fsmbi %t1.s | count 4 -; RUN: grep shli %t1.s | count 4 +; RUN: grep shli %t1.s | count 2 ; RUN: grep shlhi %t1.s | count 4 ; RUN: grep ila %t1.s | count 2 -; RUN: grep xsbh %t1.s | count 8 -; RUN: grep xshw %t1.s | count 4 +; RUN: grep xsbh %t1.s | count 4 target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128-s0:128:128" target triple = "spu" |