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| author | Chad Rosier <mcrosier@apple.com> | 2011-12-13 19:22:14 +0000 |
|---|---|---|
| committer | Chad Rosier <mcrosier@apple.com> | 2011-12-13 19:22:14 +0000 |
| commit | 8a9bce978fa4ca60d3a0ba42a1d44c41463a3c33 (patch) | |
| tree | 16921e540ea3413636954f8c94c4aa19202df488 /test/CodeGen | |
| parent | 21e1b7a13c0b1201b51304c9801a66a9f7dd7871 (diff) | |
[fast-isel] Unaligned loads of floats are not supported. Therefore, convert to a regular
load and then move the result from a GPR to a FPR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146502 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen')
| -rw-r--r-- | test/CodeGen/ARM/fast-isel.ll | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/test/CodeGen/ARM/fast-isel.ll b/test/CodeGen/ARM/fast-isel.ll index 0697460873..7fc080463a 100644 --- a/test/CodeGen/ARM/fast-isel.ll +++ b/test/CodeGen/ARM/fast-isel.ll @@ -198,3 +198,24 @@ entry: ret void } +; Check unaligned loads of floats +%class.TAlignTest = type <{ i16, float }> + +define zeroext i1 @test6(%class.TAlignTest* %this) nounwind align 2 { +entry: +; ARM: @test6 +; THUMB: @test6 + %0 = alloca %class.TAlignTest*, align 4 + store %class.TAlignTest* %this, %class.TAlignTest** %0, align 4 + %1 = load %class.TAlignTest** %0 + %2 = getelementptr inbounds %class.TAlignTest* %1, i32 0, i32 1 + %3 = load float* %2, align 1 + %4 = fcmp une float %3, 0.000000e+00 +; ARM: ldr r0, [r0, #2] +; ARM: vmov s0, r0 +; ARM: vcmpe.f32 s0, #0 +; THUMB: ldr.w r0, [r0, #2] +; THUMB: vmov s0, r0 +; THUMB: vcmpe.f32 s0, #0 + ret i1 %4 +}
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