Disable register-register preloads for NaCl.

This disables, prefetches using the base reg + index reg
("[rb, ri]") style addressing mode.
We do not allow this addressing mode for other memory
instructions either and just to make sure we would also
like to sandbox this instruction which is only possible
for the base + immediate offset addressing mode.

R=dschuff@chromium.org
BUG=https://code.google.com/p/nativeclient/issues/detail?id=3117
TEST=nacl_compiler_test/gcc-4.6.1/gcc/testsuite/gcc.c-torture/execute/builtin-prefetch-1.c
TEST=nacl_compiler_test/gcc-4.6.1/gcc/testsuite/gcc.c-torture/execute/builtin-prefetch-3.c
TEST=nacl_compiler_test/gcc-4.6.1/gcc/testsuite/gcc.c-torture/execute/builtin-prefetch-4.c
TEST=nacl_compiler_test/gcc-4.6.1/gcc/testsuite/gcc.c-torture/execute/builtin-prefetch-5.c
TEST=nacl_compiler_test/gcc-4.6.1/gcc/testsuite/gcc.c-torture/execute/builtin-prefetch-6.c
TEST=test/CodeGen/ARM/prefetch.ll

Review URL: https://codereview.chromium.org/11416141

1 files changed, 36 insertions, 0 deletions

diff --git a/test/CodeGen/ARM/prefetch.ll b/test/CodeGen/ARM/prefetch.ll
index 9c8ff2b409..8b77301273 100644
--- a/test/CodeGen/ARM/prefetch.ll
+++ b/test/CodeGen/ARM/prefetch.ll
@@ -2,6 +2,13 @@
 ; RUN: llc < %s -march=thumb -mattr=+v7         | FileCheck %s -check-prefix=THUMB2
 ; RUN: llc < %s -march=arm   -mattr=+v7         | FileCheck %s -check-prefix=ARM
 ; RUN: llc < %s -march=arm   -mcpu=cortex-a9-mp | FileCheck %s -check-prefix=ARM-MP
+; @LOCALMOD-START
+; TODO(jfb) Use -mcpu=cortex-a9-mp here, currently disabled because
+;           llvm-objdump doesn't properly disassemble pldw. binutils'
+;           objdump disassembles the instruction just fine.
+; RUN: llc < %s -mcpu=cortex-a9 -mtriple=armv7-unknown-nacl -sfi-load -filetype=obj %s -o - \
+; RUN:  | llvm-objdump -disassemble -triple armv7 - | FileCheck %s -check-prefix=ARM-NACL
+; @LOCALMOD-END
 ; rdar://8601536
 
 define void @t1(i8* %ptr) nounwind  {
@@ -17,6 +24,15 @@ entry:
 ; THUMB2: t1:
 ; THUMB2-NOT: pldw [r0]
 ; THUMB2: pld [r0]
+
+; @LOCALMOD-START
+; TODO(jfb) This pldw doesn't llvm-objdump properlu, fix this when the
+;           above-mentioned bug is fixed.
+; ARM-NACL-DISABLED-TODO-REENABLE: bic r0, r0, #3221225472
+; ARM-NACL-DISABLED-TODO-REENABLE: pldw [r0]
+; ARM-NACL: bic r0, r0, #3221225472
+; ARM-NACL: pld [r0]
+; @LOCALMOD-END
   tail call void @llvm.prefetch( i8* %ptr, i32 1, i32 3, i32 1 )
   tail call void @llvm.prefetch( i8* %ptr, i32 0, i32 3, i32 1 )
   ret void
@@ -29,6 +45,11 @@ entry:
 
 ; THUMB2: t2:
 ; THUMB2: pld [r0, #1023]
+
+; @LOCALMOD-START
+; ARM-NACL: bic r0, r0, #3221225472
+; ARM-NACL: pld [r0, #1023]
+; @LOCALMOD-END
   %tmp = getelementptr i8* %ptr, i32 1023
   tail call void @llvm.prefetch( i8* %tmp, i32 0, i32 3, i32 1 )
   ret void
@@ -42,6 +63,11 @@ entry:
 ; THUMB2: t3:
 ; THUMB2: lsrs r1, r1, #2
 ; THUMB2: pld [r0, r1]
+
+; @LOCALMOD-START
+; ARM-NACL: bic r0, r0, #3221225472
+; ARM-NACL: pld [r0]
+; @LOCALMOD-END
   %tmp1 = lshr i32 %offset, 2
   %tmp2 = add i32 %base, %tmp1
   %tmp3 = inttoptr i32 %tmp2 to i8*
@@ -56,6 +82,11 @@ entry:
 
 ; THUMB2: t4:
 ; THUMB2: pld [r0, r1, lsl #2]
+
+; @LOCALMOD-START
+; ARM-NACL: bic r0, r0, #3221225472
+; ARM-NACL: pld [r0]
+; @LOCALMOD-END
   %tmp1 = shl i32 %offset, 2
   %tmp2 = add i32 %base, %tmp1
   %tmp3 = inttoptr i32 %tmp2 to i8*
@@ -72,6 +103,11 @@ entry:
 
 ; THUMB2: t5:
 ; THUMB2: pli [r0]
+
+; @LOCALMOD-START
+; ARM-NACL: bic r0, r0, #3221225472
+; ARM-NACL: pli [r0]
+; @LOCALMOD-END
   tail call void @llvm.prefetch( i8* %ptr, i32 0, i32 3, i32 0 )
   ret void
 }