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| author | Silviu Baranga <silviu.baranga@arm.com> | 2013-01-25 10:39:49 +0000 |
|---|---|---|
| committer | Silviu Baranga <silviu.baranga@arm.com> | 2013-01-25 10:39:49 +0000 |
| commit | 4a9256f265a7fcccd1f04518b55fd751f3a920a8 (patch) | |
| tree | d061106e49ed71c03aac18de8a456782e9486a93 /test/CodeGen | |
| parent | a3bb665c6505ff78c29a37ca95dad1d297928791 (diff) | |
Fixed the condition codes for the atomic64 min/umin code generation on ARM. If the sutraction of the higher 32 bit parts gives a 0 result, we need to do the store operation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173437 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen')
| -rw-r--r-- | test/CodeGen/ARM/atomic-64bit.ll | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/test/CodeGen/ARM/atomic-64bit.ll b/test/CodeGen/ARM/atomic-64bit.ll index 69da6221b7..4ac5e5d323 100644 --- a/test/CodeGen/ARM/atomic-64bit.ll +++ b/test/CodeGen/ARM/atomic-64bit.ll @@ -133,7 +133,7 @@ define i64 @test10(i64* %ptr, i64 %val) { ; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]] ; CHECK: subs {{[a-z0-9]+}}, [[REG1]], [[REG3:(r[0-9]?[02468])]] ; CHECK: sbcs {{[a-z0-9]+}}, [[REG2]], [[REG4:(r[0-9]?[13579])]] -; CHECK: ble +; CHECK: blt ; CHECK: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]] ; CHECK: cmp ; CHECK: bne @@ -148,7 +148,7 @@ define i64 @test11(i64* %ptr, i64 %val) { ; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]] ; CHECK: subs {{[a-z0-9]+}}, [[REG1]], [[REG3:(r[0-9]?[02468])]] ; CHECK: sbcs {{[a-z0-9]+}}, [[REG2]], [[REG4:(r[0-9]?[13579])]] -; CHECK: bls +; CHECK: blo ; CHECK: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]] ; CHECK: cmp ; CHECK: bne |