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authorDan Gohman <gohman@apple.com>2009-03-13 20:42:20 +0000
committerDan Gohman <gohman@apple.com>2009-03-13 20:42:20 +0000
commit14ea1ec2324cb595f2e035bbf54ddcd483f17c11 (patch)
tree32414e0df6b4f5c9c28a4f49ed7e2990bdf511ec /test/CodeGen
parent71503710972ac747e6eaf76877cf1118d2059fce (diff)
Fix FastISel's assumption that i1 values are always zero-extended
by inserting explicit zero extensions where necessary. Included is a testcase where SelectionDAG produces a virtual register holding an i1 value which FastISel previously mistakenly assumed to be zero-extended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66941 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen')
-rw-r--r--test/CodeGen/X86/fast-isel-i1.ll19
1 files changed, 19 insertions, 0 deletions
diff --git a/test/CodeGen/X86/fast-isel-i1.ll b/test/CodeGen/X86/fast-isel-i1.ll
new file mode 100644
index 0000000000..e1ff7921a1
--- /dev/null
+++ b/test/CodeGen/X86/fast-isel-i1.ll
@@ -0,0 +1,19 @@
+; RUN: llvm-as < %s | llc -march=x86 -fast-isel | grep {andb \$1, %}
+
+declare i64 @bar(i64)
+
+define i32 @foo(i64 %x) nounwind {
+ %y = add i64 %x, -3 ; <i64> [#uses=1]
+ %t = call i64 @bar(i64 %y) ; <i64> [#uses=1]
+ %s = mul i64 %t, 77 ; <i64> [#uses=1]
+ %z = trunc i64 %s to i1 ; <i1> [#uses=1]
+ br label %next
+
+next: ; preds = %0
+ %u = zext i1 %z to i32 ; <i32> [#uses=1]
+ %v = add i32 %u, 1999 ; <i32> [#uses=1]
+ br label %exit
+
+exit: ; preds = %next
+ ret i32 %v
+}