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authorDan Gohman <gohman@apple.com>2007-11-05 23:16:33 +0000
committerDan Gohman <gohman@apple.com>2007-11-05 23:16:33 +0000
commitcff550995b2aef56a3c9956520249ac662df5696 (patch)
tree8d03823ad57ae58ff7b9dea67eb0a45181715e51 /lib
parentf1ba1cad387dc52f3c2c5afc665edf9caad00992 (diff)
Fix an abort in instcombine when folding creates a vector rem instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43743 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
-rw-r--r--lib/Transforms/Scalar/InstructionCombining.cpp14
1 files changed, 9 insertions, 5 deletions
diff --git a/lib/Transforms/Scalar/InstructionCombining.cpp b/lib/Transforms/Scalar/InstructionCombining.cpp
index 6ebf42a96d..c0ea28bd6e 100644
--- a/lib/Transforms/Scalar/InstructionCombining.cpp
+++ b/lib/Transforms/Scalar/InstructionCombining.cpp
@@ -2622,6 +2622,7 @@ Instruction *InstCombiner::visitSDiv(BinaryOperator &I) {
if (I.getType()->isInteger()) {
APInt Mask(APInt::getSignBit(I.getType()->getPrimitiveSizeInBits()));
if (MaskedValueIsZero(Op1, Mask) && MaskedValueIsZero(Op0, Mask)) {
+ // X sdiv Y -> X udiv Y, iff X and Y don't have sign bit set
return BinaryOperator::createUDiv(Op0, Op1, I.getName());
}
}
@@ -2811,6 +2812,7 @@ Instruction *InstCombiner::visitURem(BinaryOperator &I) {
Instruction *InstCombiner::visitSRem(BinaryOperator &I) {
Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1);
+ // Handle the integer rem common cases
if (Instruction *common = commonIRemTransforms(I))
return common;
@@ -2823,12 +2825,14 @@ Instruction *InstCombiner::visitSRem(BinaryOperator &I) {
return &I;
}
- // If the top bits of both operands are zero (i.e. we can prove they are
+ // If the sign bits of both operands are zero (i.e. we can prove they are
// unsigned inputs), turn this into a urem.
- APInt Mask(APInt::getSignBit(I.getType()->getPrimitiveSizeInBits()));
- if (MaskedValueIsZero(Op1, Mask) && MaskedValueIsZero(Op0, Mask)) {
- // X srem Y -> X urem Y, iff X and Y don't have sign bit set
- return BinaryOperator::createURem(Op0, Op1, I.getName());
+ if (I.getType()->isInteger()) {
+ APInt Mask(APInt::getSignBit(I.getType()->getPrimitiveSizeInBits()));
+ if (MaskedValueIsZero(Op1, Mask) && MaskedValueIsZero(Op0, Mask)) {
+ // X srem Y -> X urem Y, iff X and Y don't have sign bit set
+ return BinaryOperator::createURem(Op0, Op1, I.getName());
+ }
}
return 0;