diff options
| author | Richard Barton <richard.barton@arm.com> | 2012-07-09 16:31:14 +0000 |
|---|---|---|
| committer | Richard Barton <richard.barton@arm.com> | 2012-07-09 16:31:14 +0000 |
| commit | 8ed97ef5f6980c689a5770ec30488601201e17c3 (patch) | |
| tree | 3f523ce9f55c2c8411538e97cc244ed00bd6529d /lib | |
| parent | c985e6ece66cf2046f0113da9eb2dec331a6b09f (diff) | |
Prevent ARM assembler from losing a right shift by #32 applied to a register
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159937 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
| -rw-r--r-- | lib/Target/ARM/AsmParser/ARMAsmParser.cpp | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp index b084265e5a..790125314d 100644 --- a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp +++ b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp @@ -7247,7 +7247,9 @@ processInstruction(MCInst &Inst, case ARM::ADDrsi: newOpc = ARM::ADDrr; break; } // If the shift is by zero, use the non-shifted instruction definition. - if (ARM_AM::getSORegOffset(Inst.getOperand(3).getImm()) == 0) { + // The exception is for right shifts, where 0 == 32 + if (ARM_AM::getSORegOffset(Inst.getOperand(3).getImm()) == 0 && + !(SOpc == ARM_AM::lsr || SOpc == ARM_AM::asr)) { MCInst TmpInst; TmpInst.setOpcode(newOpc); TmpInst.addOperand(Inst.getOperand(0)); |