Rename SSARegMap -> MachineRegisterInfo in keeping with the idea

that "machine" classes are used to represent the current state of
the code being compiled.  Given this expanded name, we can start 
moving other stuff into it.  For now, move the UsedPhysRegs and
LiveIn/LoveOuts vectors from MachineFunction into it.

Update all the clients to match.

This also reduces some needless #includes, such as MachineModuleInfo
from MachineFunction.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45467 91177308-0d34-0410-b5e6-96231b3b80d8

45 files changed, 413 insertions, 396 deletions

diff --git a/lib/CodeGen/AsmPrinter.cpp b/lib/CodeGen/AsmPrinter.cpp
index fa68541249..b3643129d9 100644
--- a/lib/CodeGen/AsmPrinter.cpp
+++ b/lib/CodeGen/AsmPrinter.cpp
@@ -18,6 +18,7 @@
 #include "llvm/Module.h"
 #include "llvm/CodeGen/MachineConstantPool.h"
 #include "llvm/CodeGen/MachineJumpTableInfo.h"
+#include "llvm/CodeGen/MachineModuleInfo.h"
 #include "llvm/Support/CommandLine.h"
 #include "llvm/Support/Mangler.h"
 #include "llvm/Support/MathExtras.h"
diff --git a/lib/CodeGen/Collector.cpp b/lib/CodeGen/Collector.cpp
index 6cf253d2ff..550b52b1ff 100644
--- a/lib/CodeGen/Collector.cpp
+++ b/lib/CodeGen/Collector.cpp
@@ -21,6 +21,7 @@
 #include "llvm/CodeGen/MachineFrameInfo.h"
 #include "llvm/CodeGen/MachineFunctionPass.h"
 #include "llvm/CodeGen/MachineInstrBuilder.h"
+#include "llvm/CodeGen/MachineModuleInfo.h"
 #include "llvm/Target/TargetFrameInfo.h"
 #include "llvm/Target/TargetInstrInfo.h"
 #include "llvm/Target/TargetMachine.h"
diff --git a/lib/CodeGen/LiveIntervalAnalysis.cpp b/lib/CodeGen/LiveIntervalAnalysis.cpp
index be3dd55fc8..46cdec7bd6 100644
--- a/lib/CodeGen/LiveIntervalAnalysis.cpp
+++ b/lib/CodeGen/LiveIntervalAnalysis.cpp
@@ -23,8 +23,8 @@
 #include "llvm/CodeGen/MachineFrameInfo.h"
 #include "llvm/CodeGen/MachineInstr.h"
 #include "llvm/CodeGen/MachineLoopInfo.h"
+#include "llvm/CodeGen/MachineRegisterInfo.h"
 #include "llvm/CodeGen/Passes.h"
-#include "llvm/CodeGen/SSARegMap.h"
 #include "llvm/Target/MRegisterInfo.h"
 #include "llvm/Target/TargetInstrInfo.h"
 #include "llvm/Target/TargetMachine.h"
@@ -772,7 +772,7 @@ rewriteInstructionForSpills(const LiveInterval &li, bool TrySplit,
                  MachineInstr *ReMatOrigDefMI, MachineInstr *ReMatDefMI,
                  unsigned Slot, int LdSlot,
                  bool isLoad, bool isLoadSS, bool DefIsReMat, bool CanDelete,
-                 VirtRegMap &vrm, SSARegMap *RegMap,
+                 VirtRegMap &vrm, MachineRegisterInfo &RegInfo,
                  const TargetRegisterClass* rc,
                  SmallVector<int, 4> &ReMatIds,
                  unsigned &NewVReg, bool &HasDef, bool &HasUse,
@@ -869,7 +869,7 @@ rewriteInstructionForSpills(const LiveInterval &li, bool TrySplit,
     // Create a new virtual register for the spill interval.
     bool CreatedNewVReg = false;
     if (NewVReg == 0) {
-      NewVReg = RegMap->createVirtualRegister(rc);
+      NewVReg = RegInfo.createVirtualRegister(rc);
       vrm.grow();
       CreatedNewVReg = true;
     }
@@ -971,7 +971,7 @@ rewriteInstructionsForSpills(const LiveInterval &li, bool TrySplit,
                     MachineInstr *ReMatOrigDefMI, MachineInstr *ReMatDefMI,
                     unsigned Slot, int LdSlot,
                     bool isLoad, bool isLoadSS, bool DefIsReMat, bool CanDelete,
-                    VirtRegMap &vrm, SSARegMap *RegMap,
+                    VirtRegMap &vrm, MachineRegisterInfo &RegInfo,
                     const TargetRegisterClass* rc,
                     SmallVector<int, 4> &ReMatIds,
                     const MachineLoopInfo *loopInfo,
@@ -1043,7 +1043,7 @@ rewriteInstructionsForSpills(const LiveInterval &li, bool TrySplit,
     bool CanFold = rewriteInstructionForSpills(li, TrySplit, I->valno->id,
                                 index, end, MI, ReMatOrigDefMI, ReMatDefMI,
                                 Slot, LdSlot, isLoad, isLoadSS, DefIsReMat,
-                                CanDelete, vrm, RegMap, rc, ReMatIds, NewVReg,
+                                CanDelete, vrm, RegInfo, rc, ReMatIds, NewVReg,
                                 HasDef, HasUse, loopInfo, MBBVRegsMap, NewLIs);
     if (!HasDef && !HasUse)
       continue;
@@ -1189,8 +1189,8 @@ addIntervalsForSpills(const LiveInterval &li,
   std::map<unsigned, std::vector<SRInfo> > RestoreIdxes;
   std::map<unsigned,unsigned> MBBVRegsMap;
   std::vector<LiveInterval*> NewLIs;
-  SSARegMap *RegMap = mf_->getSSARegMap();
-  const TargetRegisterClass* rc = RegMap->getRegClass(li.reg);
+  MachineRegisterInfo &RegInfo = mf_->getRegInfo();
+  const TargetRegisterClass* rc = RegInfo.getRegClass(li.reg);
 
   unsigned NumValNums = li.getNumValNums();
   SmallVector<MachineInstr*, 4> ReMatDefs;
@@ -1235,13 +1235,13 @@ addIntervalsForSpills(const LiveInterval &li,
         // Note ReMatOrigDefMI has already been deleted.
         rewriteInstructionsForSpills(li, false, I, NULL, ReMatDefMI,
                              Slot, LdSlot, isLoad, isLoadSS, DefIsReMat,
-                             false, vrm, RegMap, rc, ReMatIds, loopInfo,
+                             false, vrm, RegInfo, rc, ReMatIds, loopInfo,
                              SpillMBBs, SpillIdxes, RestoreMBBs, RestoreIdxes,
                              MBBVRegsMap, NewLIs);
       } else {
         rewriteInstructionsForSpills(li, false, I, NULL, 0,
                              Slot, 0, false, false, false,
-                             false, vrm, RegMap, rc, ReMatIds, loopInfo,
+                             false, vrm, RegInfo, rc, ReMatIds, loopInfo,
                              SpillMBBs, SpillIdxes, RestoreMBBs, RestoreIdxes,
                              MBBVRegsMap, NewLIs);
       }
@@ -1309,7 +1309,7 @@ addIntervalsForSpills(const LiveInterval &li,
       (DefIsReMat && (ReMatDefMI->getInstrDescriptor()->Flags & M_LOAD_FLAG));
     rewriteInstructionsForSpills(li, TrySplit, I, ReMatOrigDefMI, ReMatDefMI,
                                Slot, LdSlot, isLoad, isLoadSS, DefIsReMat,
-                               CanDelete, vrm, RegMap, rc, ReMatIds, loopInfo,
+                               CanDelete, vrm, RegInfo, rc, ReMatIds, loopInfo,
                                SpillMBBs, SpillIdxes, RestoreMBBs, RestoreIdxes,
                                MBBVRegsMap, NewLIs);
   }
diff --git a/lib/CodeGen/LiveVariables.cpp b/lib/CodeGen/LiveVariables.cpp
index c4af6a86c6..e1ae37cad2 100644
--- a/lib/CodeGen/LiveVariables.cpp
+++ b/lib/CodeGen/LiveVariables.cpp
@@ -28,6 +28,7 @@
 
 #include "llvm/CodeGen/LiveVariables.h"
 #include "llvm/CodeGen/MachineInstr.h"
+#include "llvm/CodeGen/MachineRegisterInfo.h"
 #include "llvm/Target/MRegisterInfo.h"
 #include "llvm/Target/TargetInstrInfo.h"
 #include "llvm/Target/TargetMachine.h"
@@ -537,8 +538,9 @@ bool LiveVariables::runOnMachineFunction(MachineFunction &mf) {
     // it as using all of the live-out values in the function.
     if (!MBB->empty() && TII.isReturn(MBB->back().getOpcode())) {
       MachineInstr *Ret = &MBB->back();
-      for (MachineFunction::liveout_iterator I = MF->liveout_begin(),
-             E = MF->liveout_end(); I != E; ++I) {
+      for (MachineRegisterInfo::liveout_iterator
+           I = MF->getRegInfo().liveout_begin(),
+           E = MF->getRegInfo().liveout_end(); I != E; ++I) {
         assert(MRegisterInfo::isPhysicalRegister(*I) &&
                "Cannot have a live-in virtual register!");
         HandlePhysRegUse(*I, Ret);
diff --git a/lib/CodeGen/LowerSubregs.cpp b/lib/CodeGen/LowerSubregs.cpp
index a0db5c5865..668a9e5540 100644
--- a/lib/CodeGen/LowerSubregs.cpp
+++ b/lib/CodeGen/LowerSubregs.cpp
@@ -12,7 +12,7 @@
 #include "llvm/Function.h"
 #include "llvm/CodeGen/MachineFunctionPass.h"
 #include "llvm/CodeGen/MachineInstr.h"
-#include "llvm/CodeGen/SSARegMap.h"
+#include "llvm/CodeGen/MachineRegisterInfo.h"
 #include "llvm/Target/MRegisterInfo.h"
 #include "llvm/Target/TargetInstrInfo.h"
 #include "llvm/Target/TargetMachine.h"
@@ -83,7 +83,7 @@ bool LowerSubregsInstructionPass::LowerExtract(MachineInstr *MI) {
      if (MRegisterInfo::isPhysicalRegister(DstReg)) {
        TRC = getPhysicalRegisterRegClass(MRI, DstReg);
      } else {
-       TRC = MF.getSSARegMap()->getRegClass(DstReg);
+       TRC = MF.getRegInfo().getRegClass(DstReg);
      }
      assert(TRC == getPhysicalRegisterRegClass(MRI, SrcReg) &&
              "Extract subreg and Dst must be of same register class");
@@ -155,7 +155,7 @@ bool LowerSubregsInstructionPass::LowerInsert(MachineInstr *MI) {
       if (MRegisterInfo::isPhysicalRegister(InsReg)) {
         TRC1 = getPhysicalRegisterRegClass(MRI, InsReg);
       } else {
-        TRC1 = MF.getSSARegMap()->getRegClass(InsReg);
+        TRC1 = MF.getRegInfo().getRegClass(InsReg);
       }
       MRI.copyRegToReg(*MBB, MI, DstSubReg, InsReg, TRC1, TRC1);
 
@@ -179,7 +179,7 @@ bool LowerSubregsInstructionPass::LowerInsert(MachineInstr *MI) {
     if (MRegisterInfo::isPhysicalRegister(DstReg)) {
       TRC0 = getPhysicalRegisterRegClass(MRI, DstReg);
     } else {
-      TRC0 = MF.getSSARegMap()->getRegClass(DstReg);
+      TRC0 = MF.getRegInfo().getRegClass(DstReg);
     }
     assert(TRC0 == getPhysicalRegisterRegClass(MRI, SrcReg) &&
             "Insert superreg and Dst must be of same register class");
@@ -204,7 +204,7 @@ bool LowerSubregsInstructionPass::LowerInsert(MachineInstr *MI) {
     if (MRegisterInfo::isPhysicalRegister(InsReg)) {
       TRC1 = getPhysicalRegisterRegClass(MRI, InsReg);
     } else {
-      TRC1 = MF.getSSARegMap()->getRegClass(InsReg);
+      TRC1 = MF.getRegInfo().getRegClass(InsReg);
     }
     MRI.copyRegToReg(*MBB, MI, DstSubReg, InsReg, TRC1, TRC1);
 
diff --git a/lib/CodeGen/MachineFunction.cpp b/lib/CodeGen/MachineFunction.cpp
index 037e3e483f..595159b15f 100644
--- a/lib/CodeGen/MachineFunction.cpp
+++ b/lib/CodeGen/MachineFunction.cpp
@@ -14,12 +14,12 @@
 //===----------------------------------------------------------------------===//
 
 #include "llvm/DerivedTypes.h"
+#include "llvm/CodeGen/MachineConstantPool.h"
 #include "llvm/CodeGen/MachineFunctionPass.h"
-#include "llvm/CodeGen/MachineInstr.h"
-#include "llvm/CodeGen/SSARegMap.h"
 #include "llvm/CodeGen/MachineFrameInfo.h"
-#include "llvm/CodeGen/MachineConstantPool.h"
+#include "llvm/CodeGen/MachineInstr.h"
 #include "llvm/CodeGen/MachineJumpTableInfo.h"
+#include "llvm/CodeGen/MachineRegisterInfo.h"
 #include "llvm/CodeGen/Passes.h"
 #include "llvm/Target/TargetData.h"
 #include "llvm/Target/TargetLowering.h"
@@ -122,11 +122,10 @@ void ilist_traits<MachineBasicBlock>::transferNodesFromList(
 MachineFunction::MachineFunction(const Function *F,
                                  const TargetMachine &TM)
   : Annotation(MF_AID), Fn(F), Target(TM) {
-  SSARegMapping = new SSARegMap();
+  RegInfo = new MachineRegisterInfo(*TM.getRegisterInfo());
   MFInfo = 0;
   FrameInfo = new MachineFrameInfo();
   ConstantPool = new MachineConstantPool(TM.getTargetData());
-  UsedPhysRegs.resize(TM.getRegisterInfo()->getNumRegs());
   
   // Set up jump table.
   const TargetData &TD = *TM.getTargetData();
@@ -141,7 +140,7 @@ MachineFunction::MachineFunction(const Function *F,
 
 MachineFunction::~MachineFunction() {
   BasicBlocks.clear();
-  delete SSARegMapping;
+  delete RegInfo;
   delete MFInfo;
   delete FrameInfo;
   delete ConstantPool;
@@ -208,9 +207,10 @@ void MachineFunction::print(std::ostream &OS) const {
   
   const MRegisterInfo *MRI = getTarget().getRegisterInfo();
   
-  if (!livein_empty()) {
+  if (!RegInfo->livein_empty()) {
     OS << "Live Ins:";
-    for (livein_iterator I = livein_begin(), E = livein_end(); I != E; ++I) {
+    for (MachineRegisterInfo::livein_iterator
+         I = RegInfo->livein_begin(), E = RegInfo->livein_end(); I != E; ++I) {
       if (MRI)
         OS << " " << MRI->getName(I->first);
       else
@@ -221,9 +221,10 @@ void MachineFunction::print(std::ostream &OS) const {
     }
     OS << "\n";
   }
-  if (!liveout_empty()) {
+  if (!RegInfo->liveout_empty()) {
     OS << "Live Outs:";
-    for (liveout_iterator I = liveout_begin(), E = liveout_end(); I != E; ++I)
+    for (MachineRegisterInfo::liveout_iterator
+         I = RegInfo->liveout_begin(), E = RegInfo->liveout_end(); I != E; ++I)
       if (MRI)
         OS << " " << MRI->getName(*I);
       else
@@ -324,11 +325,6 @@ MachineFunction& MachineFunction::get(const Function *F)
   return *mc;
 }
 
-void MachineFunction::clearSSARegMap() {
-  delete SSARegMapping;
-  SSARegMapping = 0;
-}
-
 //===----------------------------------------------------------------------===//
 //  MachineFrameInfo implementation
 //===----------------------------------------------------------------------===//
diff --git a/lib/CodeGen/MachineInstr.cpp b/lib/CodeGen/MachineInstr.cpp
index d843b27c49..95c768d72c 100644
--- a/lib/CodeGen/MachineInstr.cpp
+++ b/lib/CodeGen/MachineInstr.cpp
@@ -12,6 +12,7 @@
 //===----------------------------------------------------------------------===//
 
 #include "llvm/CodeGen/MachineInstr.h"
+#include "llvm/Value.h"
 #include "llvm/CodeGen/MachineFunction.h"
 #include "llvm/Target/TargetMachine.h"
 #include "llvm/Target/TargetInstrInfo.h"
diff --git a/lib/CodeGen/MachineRegisterInfo.cpp b/lib/CodeGen/MachineRegisterInfo.cpp
new file mode 100644
index 0000000000..19c09eee51
--- /dev/null
+++ b/lib/CodeGen/MachineRegisterInfo.cpp
@@ -0,0 +1,20 @@
+//===-- MachineRegisterInfo.cpp -------------------------------------------===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// Implementation of the MachineRegisterInfo class.
+//
+//===----------------------------------------------------------------------===//
+
+#include "llvm/CodeGen/MachineRegisterInfo.h"
+using namespace llvm;
+
+MachineRegisterInfo::MachineRegisterInfo(const MRegisterInfo &MRI) {
+  VRegInfo.reserve(256);
+  UsedPhysRegs.resize(MRI.getNumRegs());
+}
diff --git a/lib/CodeGen/PHIElimination.cpp b/lib/CodeGen/PHIElimination.cpp
index 480ba939b0..764e89b6da 100644
--- a/lib/CodeGen/PHIElimination.cpp
+++ b/lib/CodeGen/PHIElimination.cpp
@@ -18,7 +18,7 @@
 #include "llvm/CodeGen/Passes.h"
 #include "llvm/CodeGen/MachineFunctionPass.h"
 #include "llvm/CodeGen/MachineInstr.h"
-#include "llvm/CodeGen/SSARegMap.h"
+#include "llvm/CodeGen/MachineRegisterInfo.h"
 #include "llvm/Target/TargetInstrInfo.h"
 #include "llvm/Target/TargetMachine.h"
 #include "llvm/ADT/STLExtras.h"
@@ -127,8 +127,8 @@ void PNE::LowerAtomicPHINode(MachineBasicBlock &MBB,
 
   // Create a new register for the incoming PHI arguments.
   MachineFunction &MF = *MBB.getParent();
-  const TargetRegisterClass *RC = MF.getSSARegMap()->getRegClass(DestReg);
-  unsigned IncomingReg = MF.getSSARegMap()->createVirtualRegister(RC);
+  const TargetRegisterClass *RC = MF.getRegInfo().getRegClass(DestReg);
+  unsigned IncomingReg = MF.getRegInfo().createVirtualRegister(RC);
 
   // Insert a register to register copy in the top of the current block (but
   // after any remaining phi nodes) which copies the new incoming register
diff --git a/lib/CodeGen/PrologEpilogInserter.cpp b/lib/CodeGen/PrologEpilogInserter.cpp
index 3f62630b3b..d1f796d47d 100644
--- a/lib/CodeGen/PrologEpilogInserter.cpp
+++ b/lib/CodeGen/PrologEpilogInserter.cpp
@@ -20,6 +20,8 @@
 #include "llvm/CodeGen/MachineFunctionPass.h"
 #include "llvm/CodeGen/MachineInstr.h"
 #include "llvm/CodeGen/MachineFrameInfo.h"
+#include "llvm/CodeGen/MachineModuleInfo.h"
+#include "llvm/CodeGen/MachineRegisterInfo.h"
 #include "llvm/CodeGen/RegisterScavenging.h"
 #include "llvm/Target/TargetMachine.h"
 #include "llvm/Target/MRegisterInfo.h"
@@ -48,9 +50,8 @@ namespace {
 
       // Get MachineModuleInfo so that we can track the construction of the
       // frame.
-      if (MachineModuleInfo *MMI = getAnalysisToUpdate<MachineModuleInfo>()) {
+      if (MachineModuleInfo *MMI = getAnalysisToUpdate<MachineModuleInfo>())
         Fn.getFrameInfo()->setMachineModuleInfo(MMI);
-      }
 
       // Allow the target machine to make some adjustments to the function
       // e.g. UsedPhysRegs before calculateCalleeSavedRegisters.
@@ -174,13 +175,13 @@ void PEI::calculateCalleeSavedRegisters(MachineFunction &Fn) {
   std::vector<CalleeSavedInfo> CSI;
   for (unsigned i = 0; CSRegs[i]; ++i) {
     unsigned Reg = CSRegs[i];
-    if (Fn.isPhysRegUsed(Reg)) {
+    if (Fn.getRegInfo().isPhysRegUsed(Reg)) {
         // If the reg is modified, save it!
       CSI.push_back(CalleeSavedInfo(Reg, CSRegClasses[i]));
     } else {
       for (const unsigned *AliasSet = RegInfo->getAliasSet(Reg);
            *AliasSet; ++AliasSet) {  // Check alias registers too.
-        if (Fn.isPhysRegUsed(*AliasSet)) {
+        if (Fn.getRegInfo().isPhysRegUsed(*AliasSet)) {
           CSI.push_back(CalleeSavedInfo(Reg, CSRegClasses[i]));
           break;
         }
diff --git a/lib/CodeGen/RegAllocBigBlock.cpp b/lib/CodeGen/RegAllocBigBlock.cpp
index 3e9254ab9d..5c894729a7 100644
--- a/lib/CodeGen/RegAllocBigBlock.cpp
+++ b/lib/CodeGen/RegAllocBigBlock.cpp
@@ -32,8 +32,8 @@
 #include "llvm/CodeGen/Passes.h"
 #include "llvm/CodeGen/MachineFunctionPass.h"
 #include "llvm/CodeGen/MachineInstr.h"
-#include "llvm/CodeGen/SSARegMap.h"
 #include "llvm/CodeGen/MachineFrameInfo.h"
+#include "llvm/CodeGen/MachineRegisterInfo.h"
 #include "llvm/CodeGen/LiveVariables.h"
 #include "llvm/CodeGen/RegAllocRegistry.h"
 #include "llvm/Target/TargetInstrInfo.h"
@@ -326,7 +326,7 @@ void RABigBlock::spillVirtReg(MachineBasicBlock &MBB,
   // register.  We only need to spill it into its stack slot if it has been
   // modified.
   if (isVirtRegModified(VirtReg)) {
-    const TargetRegisterClass *RC = MF->getSSARegMap()->getRegClass(VirtReg);
+    const TargetRegisterClass *RC = MF->getRegInfo().getRegClass(VirtReg);
     int FrameIndex = getStackSpaceFor(VirtReg, RC);
     DOUT << " to stack slot #" << FrameIndex;
     RegInfo->storeRegToStackSlot(MBB, I, PhysReg, true, FrameIndex, RC);
@@ -418,7 +418,7 @@ unsigned RABigBlock::getFreeReg(const TargetRegisterClass *RC) {
 ///
 unsigned RABigBlock::chooseReg(MachineBasicBlock &MBB, MachineInstr *I,
                          unsigned VirtReg) {
-  const TargetRegisterClass *RC = MF->getSSARegMap()->getRegClass(VirtReg);
+  const TargetRegisterClass *RC = MF->getRegInfo().getRegClass(VirtReg);
   // First check to see if we have a free register of the requested type...
   unsigned PhysReg = getFreeReg(RC);
 
@@ -512,7 +512,7 @@ MachineInstr *RABigBlock::reloadVirtReg(MachineBasicBlock &MBB, MachineInstr *MI
 
   // Otherwise, if we have free physical registers available to hold the
   // value, use them.
-  const TargetRegisterClass *RC = MF->getSSARegMap()->getRegClass(VirtReg);
+  const TargetRegisterClass *RC = MF->getRegInfo().getRegClass(VirtReg);
   unsigned PhysReg = getFreeReg(RC);
   int FrameIndex = getStackSpaceFor(VirtReg, RC);
 
@@ -545,7 +545,7 @@ MachineInstr *RABigBlock::reloadVirtReg(MachineBasicBlock &MBB, MachineInstr *MI
   RegInfo->loadRegFromStackSlot(MBB, MI, PhysReg, FrameIndex, RC);
   ++NumLoads;    // Update statistics
 
-  MF->setPhysRegUsed(PhysReg);
+  MF->getRegInfo().setPhysRegUsed(PhysReg);
   MI->getOperand(OpNum).setReg(PhysReg);  // Assign the input register
   return MI;
 }
@@ -624,16 +624,17 @@ void RABigBlock::AllocateBasicBlock(MachineBasicBlock &MBB) {
   // If this is the first basic block in the machine function, add live-in
   // registers as active.
   if (&MBB == &*MF->begin()) {
-    for (MachineFunction::livein_iterator I = MF->livein_begin(),
-         E = MF->livein_end(); I != E; ++I) {
+    for (MachineRegisterInfo::livein_iterator
+         I = MF->getRegInfo().livein_begin(),
+         E = MF->getRegInfo().livein_end(); I != E; ++I) {
       unsigned Reg = I->first;
-      MF->setPhysRegUsed(Reg);
+      MF->getRegInfo().setPhysRegUsed(Reg);
       PhysRegsUsed[Reg] = 0;            // It is free and reserved now
       for (const unsigned *AliasSet = RegInfo->getSubRegisters(Reg);
            *AliasSet; ++AliasSet) {
         if (PhysRegsUsed[*AliasSet] != -2) {
           PhysRegsUsed[*AliasSet] = 0;  // It is free and reserved now
-          MF->setPhysRegUsed(*AliasSet);
+          MF->getRegInfo().setPhysRegUsed(*AliasSet);
         }
       }
     }    
@@ -731,14 +732,14 @@ void RABigBlock::AllocateBasicBlock(MachineBasicBlock &MBB) {
         // larger registers). Ignore.
         if (isReadModWriteImplicitDef(MI, MO.getReg())) continue;
 
-        MF->setPhysRegUsed(Reg);
+        MF->getRegInfo().setPhysRegUsed(Reg);
         spillPhysReg(MBB, MI, Reg, true); // Spill any existing value in reg
         PhysRegsUsed[Reg] = 0;            // It is free and reserved now
         for (const unsigned *AliasSet = RegInfo->getSubRegisters(Reg);
              *AliasSet; ++AliasSet) {
           if (PhysRegsUsed[*AliasSet] != -2) {
             PhysRegsUsed[*AliasSet] = 0;  // It is free and reserved now
-            MF->setPhysRegUsed(*AliasSet);
+            MF->getRegInfo().setPhysRegUsed(*AliasSet);
           }
         }
       }
@@ -753,12 +754,12 @@ void RABigBlock::AllocateBasicBlock(MachineBasicBlock &MBB) {
           spillPhysReg(MBB, MI, Reg, true);
           PhysRegsUsed[Reg] = 0;            // It is free and reserved now
         }
-        MF->setPhysRegUsed(Reg);
+        MF->getRegInfo().setPhysRegUsed(Reg);
         for (const unsigned *AliasSet = RegInfo->getSubRegisters(Reg);
              *AliasSet; ++AliasSet) {
           if (PhysRegsUsed[*AliasSet] != -2) {
             PhysRegsUsed[*AliasSet] = 0;  // It is free and reserved now
-            MF->setPhysRegUsed(*AliasSet);
+            MF->getRegInfo().setPhysRegUsed(*AliasSet);
           }
         }
       }
@@ -786,7 +787,7 @@ void RABigBlock::AllocateBasicBlock(MachineBasicBlock &MBB) {
         // If DestVirtReg already has a value, use it.
         if (!(DestPhysReg = getVirt2PhysRegMapSlot(DestVirtReg)))
           DestPhysReg = chooseReg(MBB, MI, DestVirtReg);
-        MF->setPhysRegUsed(DestPhysReg);
+        MF->getRegInfo().setPhysRegUsed(DestPhysReg);
         markVirtRegModified(DestVirtReg);
         MI->getOperand(i).setReg(DestPhysReg);  // Assign the output register
       }
@@ -868,9 +869,10 @@ bool RABigBlock::runOnMachineFunction(MachineFunction &Fn) {
 
   // initialize the virtual->physical register map to have a 'null'
   // mapping for all virtual registers
-  Virt2PhysRegMap.grow(MF->getSSARegMap()->getLastVirtReg());
-  StackSlotForVirtReg.grow(MF->getSSARegMap()->getLastVirtReg());
-  VirtRegModified.resize(MF->getSSARegMap()->getLastVirtReg() - MRegisterInfo::FirstVirtualRegister + 1,0);
+  Virt2PhysRegMap.grow(MF->getRegInfo().getLastVirtReg());
+  StackSlotForVirtReg.grow(MF->getRegInfo().getLastVirtReg());
+  VirtRegModified.resize(MF->getRegInfo().getLastVirtReg() - 
+                         MRegisterInfo::FirstVirtualRegister + 1, 0);
 
   // Loop over all of the basic blocks, eliminating virtual register references
   for (MachineFunction::iterator MBB = Fn.begin(), MBBe = Fn.end();
diff --git a/lib/CodeGen/RegAllocLinearScan.cpp b/lib/CodeGen/RegAllocLinearScan.cpp
index 7cf4ddf27d..17d416a4a6 100644
--- a/lib/CodeGen/RegAllocLinearScan.cpp
+++ b/lib/CodeGen/RegAllocLinearScan.cpp
@@ -19,10 +19,10 @@
 #include "llvm/CodeGen/MachineFunctionPass.h"
 #include "llvm/CodeGen/MachineInstr.h"
 #include "llvm/CodeGen/MachineLoopInfo.h"
+#include "llvm/CodeGen/MachineRegisterInfo.h"
 #include "llvm/CodeGen/Passes.h"
 #include "llvm/CodeGen/RegAllocRegistry.h"
 #include "llvm/CodeGen/RegisterCoalescer.h"
-#include "llvm/CodeGen/SSARegMap.h"
 #include "llvm/Target/MRegisterInfo.h"
 #include "llvm/Target/TargetMachine.h"
 #include "llvm/Target/TargetInstrInfo.h"
@@ -64,7 +64,7 @@ namespace {
     const TargetMachine* tm_;
     const MRegisterInfo* mri_;
     const TargetInstrInfo* tii_;
-    SSARegMap *regmap_;
+    MachineRegisterInfo *reginfo_;
     BitVector allocatableRegs_;
     LiveIntervals* li_;
     const MachineLoopInfo *loopInfo;
@@ -230,7 +230,7 @@ unsigned RALinScan::attemptTrivialCoalescing(LiveInterval &cur, unsigned Reg) {
   if (Reg == SrcReg)
     return Reg;
 
-  const TargetRegisterClass *RC = regmap_->getRegClass(cur.reg);
+  const TargetRegisterClass *RC = reginfo_->getRegClass(cur.reg);
   if (!RC->contains(SrcReg))
     return Reg;
 
@@ -251,7 +251,7 @@ bool RALinScan::runOnMachineFunction(MachineFunction &fn) {
   tm_ = &fn.getTarget();
   mri_ = tm_->getRegisterInfo();
   tii_ = tm_->getInstrInfo();
-  regmap_ = mf_->getSSARegMap();
+  reginfo_ = &mf_->getRegInfo();
   allocatableRegs_ = mri_->getAllocatableSet(fn);
   li_ = &getAnalysis<LiveIntervals>();
   loopInfo = &getAnalysis<MachineLoopInfo>();
@@ -296,7 +296,7 @@ void RALinScan::initIntervalSets()
 
   for (LiveIntervals::iterator i = li_->begin(), e = li_->end(); i != e; ++i) {
     if (MRegisterInfo::isPhysicalRegister(i->second.reg)) {
-      mf_->setPhysRegUsed(i->second.reg);
+      reginfo_->setPhysRegUsed(i->second.reg);
       fixed_.push_back(std::make_pair(&i->second, i->second.begin()));
     } else