diff options
author | Dan Gohman <gohman@apple.com> | 2008-02-06 22:27:42 +0000 |
---|---|---|
committer | Dan Gohman <gohman@apple.com> | 2008-02-06 22:27:42 +0000 |
commit | 69de1932b350d7cdfc0ed1f4198d6f78c7822a02 (patch) | |
tree | 9509f355cd39a5d69988db1d878c213d0526011d /lib | |
parent | b745e88bf0a6d7f51a336cd6158824e7383e8d24 (diff) |
Re-apply the memory operand changes, with a fix for the static
initializer problem, a minor tweak to the way the
DAGISelEmitter finds load/store nodes, and a renaming of the
new PseudoSourceValue objects.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46827 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
-rw-r--r-- | lib/CodeGen/MachineInstr.cpp | 31 | ||||
-rw-r--r-- | lib/CodeGen/PseudoSourceValue.cpp | 41 | ||||
-rw-r--r-- | lib/CodeGen/SelectionDAG/LegalizeDAG.cpp | 108 | ||||
-rw-r--r-- | lib/CodeGen/SelectionDAG/ScheduleDAG.cpp | 28 | ||||
-rw-r--r-- | lib/CodeGen/SelectionDAG/SelectionDAG.cpp | 76 | ||||
-rw-r--r-- | lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp | 9 | ||||
-rw-r--r-- | lib/Target/ARM/ARMISelLowering.cpp | 5 | ||||
-rw-r--r-- | lib/Target/Alpha/AlphaISelLowering.cpp | 20 | ||||
-rw-r--r-- | lib/Target/IA64/IA64ISelLowering.cpp | 11 | ||||
-rw-r--r-- | lib/Target/PowerPC/PPCISelLowering.cpp | 48 | ||||
-rw-r--r-- | lib/Target/Sparc/SparcISelDAGToDAG.cpp | 12 | ||||
-rw-r--r-- | lib/Target/X86/X86ISelLowering.cpp | 100 |
12 files changed, 345 insertions, 144 deletions
diff --git a/lib/CodeGen/MachineInstr.cpp b/lib/CodeGen/MachineInstr.cpp index e1e2336b50..c455b024e3 100644 --- a/lib/CodeGen/MachineInstr.cpp +++ b/lib/CodeGen/MachineInstr.cpp @@ -15,6 +15,8 @@ #include "llvm/Value.h" #include "llvm/CodeGen/MachineFunction.h" #include "llvm/CodeGen/MachineRegisterInfo.h" +#include "llvm/CodeGen/PseudoSourceValue.h" +#include "llvm/CodeGen/SelectionDAGNodes.h" #include "llvm/Target/TargetMachine.h" #include "llvm/Target/TargetInstrInfo.h" #include "llvm/Target/TargetInstrDesc.h" @@ -292,6 +294,7 @@ MachineInstr::MachineInstr(const MachineInstr &MI) { TID = &MI.getDesc(); NumImplicitOps = MI.NumImplicitOps; Operands.reserve(MI.getNumOperands()); + MemOperands = MI.MemOperands; // Add operands for (unsigned i = 0; i != MI.getNumOperands(); ++i) { @@ -627,6 +630,34 @@ void MachineInstr::print(std::ostream &OS, const TargetMachine *TM) const { getOperand(i).print(OS, TM); } + if (getNumMemOperands() > 0) { + OS << ", SV:"; + for (unsigned i = 0; i < getNumMemOperands(); i++) { + const MemOperand &MRO = getMemOperand(i); + const Value *V = MRO.getValue(); + + assert(V && "SV missing."); + assert((MRO.isLoad() || MRO.isStore()) && + "SV has to be a load, store or both."); + + if (MRO.isVolatile()) + OS << "Volatile "; + if (MRO.isLoad()) + OS << "LD "; + if (MRO.isStore()) + OS << "ST "; + + OS << MRO.getSize(); + + if (!V->getName().empty()) + OS << "[" << V->getName() << " + " << MRO.getOffset() << "]"; + else if (isa<PseudoSourceValue>(V)) + OS << "[" << *V << " + " << MRO.getOffset() << "]"; + else + OS << "[" << V << " + " << MRO.getOffset() << "]"; + } + } + OS << "\n"; } diff --git a/lib/CodeGen/PseudoSourceValue.cpp b/lib/CodeGen/PseudoSourceValue.cpp index e69de29bb2..b7fb25e4f1 100644 --- a/lib/CodeGen/PseudoSourceValue.cpp +++ b/lib/CodeGen/PseudoSourceValue.cpp @@ -0,0 +1,41 @@ +//===-- llvm/CodeGen/PseudoSourceValue.cpp ----------------------*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file implements the PseudoSourceValue class. +// +//===----------------------------------------------------------------------===// + +#include "llvm/CodeGen/PseudoSourceValue.h" +#include "llvm/DerivedTypes.h" +#include "llvm/Support/ManagedStatic.h" + +namespace llvm { + static ManagedStatic<PseudoSourceValue[5]> PSVs; + + const PseudoSourceValue &PseudoSourceValue::getFixedStack() { return (*PSVs)[0]; } + const PseudoSourceValue &PseudoSourceValue::getStack() { return (*PSVs)[1]; } + const PseudoSourceValue &PseudoSourceValue::getGOT() { return (*PSVs)[2]; } + const PseudoSourceValue &PseudoSourceValue::getConstantPool() { return (*PSVs)[3]; } + const PseudoSourceValue &PseudoSourceValue::getJumpTable() { return (*PSVs)[4]; } + + static const char *PSVNames[] = { + "FixedStack", + "Stack", + "GOT", + "ConstantPool", + "JumpTable" + }; + + PseudoSourceValue::PseudoSourceValue() : + Value(PointerType::getUnqual(Type::Int8Ty), PseudoSourceValueVal) {} + + void PseudoSourceValue::print(std::ostream &OS) const { + OS << PSVNames[this - *PSVs]; + } +} diff --git a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp index 4749b76344..71633fe7cd 100644 --- a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp +++ b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp @@ -16,6 +16,7 @@ #include "llvm/CodeGen/MachineFrameInfo.h" #include "llvm/CodeGen/MachineJumpTableInfo.h" #include "llvm/CodeGen/MachineModuleInfo.h" +#include "llvm/CodeGen/PseudoSourceValue.h" #include "llvm/Target/TargetFrameInfo.h" #include "llvm/Target/TargetLowering.h" #include "llvm/Target/TargetData.h" @@ -509,9 +510,11 @@ static SDOperand ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP, SDOperand CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy()); if (Extend) { return DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(), - CPIdx, NULL, 0, MVT::f32); + CPIdx, &PseudoSourceValue::getConstantPool(), + 0, MVT::f32); } else { - return DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, NULL, 0); + return DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, + &PseudoSourceValue::getConstantPool(), 0); } } @@ -796,6 +799,7 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { case ISD::TargetExternalSymbol: case ISD::VALUETYPE: case ISD::SRCVALUE: + case ISD::MEMOPERAND: case ISD::STRING: case ISD::CONDCODE: // Primitives must all be legal. @@ -1316,8 +1320,15 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { MVT::ValueType IdxVT = Tmp3.getValueType(); MVT::ValueType PtrVT = TLI.getPointerTy(); SDOperand StackPtr = DAG.CreateStackTemporary(VT); + + FrameIndexSDNode *StackPtrFI = dyn_cast<FrameIndexSDNode>(StackPtr.Val); + assert(StackPtrFI); + int SPFI = StackPtrFI->getIndex(); + // Store the vector. - SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Tmp1, StackPtr, NULL, 0); + SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Tmp1, StackPtr, + &PseudoSourceValue::getFixedStack(), + SPFI); // Truncate or zero extend offset to target pointer type. unsigned CastOpc = (IdxVT > PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND; @@ -1327,9 +1338,11 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { Tmp3 = DAG.getNode(ISD::MUL, IdxVT, Tmp3,DAG.getConstant(EltSize, IdxVT)); SDOperand StackPtr2 = DAG.getNode(ISD::ADD, IdxVT, Tmp3, StackPtr); // Store the scalar value. - Ch = DAG.getStore(Ch, Tmp2, StackPtr2, NULL, 0); + Ch = DAG.getStore(Ch, Tmp2, StackPtr2, + &PseudoSourceValue::getFixedStack(), SPFI); // Load the updated vector. - Result = DAG.getLoad(VT, Ch, StackPtr, NULL, 0); + Result = DAG.getLoad(VT, Ch, StackPtr, + &PseudoSourceValue::getFixedStack(), SPFI); break; } } @@ -1678,8 +1691,10 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { SDOperand LD; switch (EntrySize) { default: assert(0 && "Size of jump table not supported yet."); break; - case 4: LD = DAG.getLoad(MVT::i32, Chain, Addr, NULL, 0); break; - case 8: LD = DAG.getLoad(MVT::i64, Chain, Addr, NULL, 0); break; + case 4: LD = DAG.getLoad(MVT::i32, Chain, Addr, + &PseudoSourceValue::getJumpTable(), 0); break; + case 8: LD = DAG.getLoad(MVT::i64, Chain, Addr, + &PseudoSourceValue::getJumpTable(), 0); break; } Addr = LD; @@ -3240,16 +3255,14 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { } break; case TargetLowering::Expand: { - SrcValueSDNode *SV = cast<SrcValueSDNode>(Node->getOperand(2)); - SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2, - SV->getValue(), SV->getOffset()); + const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue(); + SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2, V, 0); // Increment the pointer, VAList, to the next vaarg Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList, DAG.getConstant(MVT::getSizeInBits(VT)/8, TLI.getPointerTy())); // Store the incremented VAList to the legalized pointer - Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, SV->getValue(), - SV->getOffset()); + Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, V, 0); // Load the actual argument out of the pointer VAList Result = DAG.getLoad(VT, Tmp3, VAList, NULL, 0); Tmp1 = LegalizeOp(Result.getValue(1)); @@ -3285,12 +3298,10 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { case TargetLowering::Expand: // This defaults to loading a pointer from the input and storing it to the // output, returning the chain. - SrcValueSDNode *SVD = cast<SrcValueSDNode>(Node->getOperand(3)); - SrcValueSDNode *SVS = cast<SrcValueSDNode>(Node->getOperand(4)); - Tmp4 = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp3, SVD->getValue(), - SVD->getOffset()); - Result = DAG.getStore(Tmp4.getValue(1), Tmp4, Tmp2, SVS->getValue(), - SVS->getOffset()); + const Value *VD = cast<SrcValueSDNode>(Node->getOperand(3))->getValue(); + const Value *VS = cast<SrcValueSDNode>(Node->getOperand(4))->getValue(); + Tmp4 = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp3, VD, 0); + Result = DAG.getStore(Tmp4.getValue(1), Tmp4, Tmp2, VS, 0); break; } break; @@ -4285,16 +4296,14 @@ SDOperand SelectionDAGLegalize::PromoteOp(SDOperand Op) { Tmp3 = DAG.getVAArg(VT, Tmp1, Tmp2, Node->getOperand(2)); Result = TLI.CustomPromoteOperation(Tmp3, DAG); } else { - SrcValueSDNode *SV = cast<SrcValueSDNode>(Node->getOperand(2)); - SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2, - SV->getValue(), SV->getOffset()); + const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue(); + SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2, V, 0); // Increment the pointer, VAList, to the next vaarg Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList, DAG.getConstant(MVT::getSizeInBits(VT)/8, TLI.getPointerTy())); // Store the incremented VAList to the legalized pointer - Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, SV->getValue(), - SV->getOffset()); + Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, V, 0); // Load the actual argument out of the pointer VAList Result = DAG.getExtLoad(ISD::EXTLOAD, NVT, Tmp3, VAList, NULL, 0, VT); } @@ -4750,6 +4759,10 @@ SDOperand SelectionDAGLegalize::EmitStackConvert(SDOperand SrcOp, // Create the stack frame object. SDOperand FIPtr = DAG.CreateStackTemporary(SlotVT); + FrameIndexSDNode *StackPtrFI = dyn_cast<FrameIndexSDNode>(FIPtr); + assert(StackPtrFI); + int SPFI = StackPtrFI->getIndex(); + unsigned SrcSize = MVT::getSizeInBits(SrcOp.getValueType()); unsigned SlotSize = MVT::getSizeInBits(SlotVT); unsigned DestSize = MVT::getSizeInBits(DestVT); @@ -4758,10 +4771,14 @@ SDOperand SelectionDAGLegalize::EmitStackConvert(SDOperand SrcOp, // later than DestVT. SDOperand Store; if (SrcSize > SlotSize) - Store = DAG.getTruncStore(DAG.getEntryNode(), SrcOp, FIPtr, NULL, 0,SlotVT); + Store = DAG.getTruncStore(DAG.getEntryNode(), SrcOp, FIPtr, + &PseudoSourceValue::getFixedStack(), + SPFI, SlotVT); else { assert(SrcSize == SlotSize && "Invalid store"); - Store = DAG.getStore(DAG.getEntryNode(), SrcOp, FIPtr, NULL, 0); + Store = DAG.getStore(DAG.getEntryNode(), SrcOp, FIPtr, + &PseudoSourceValue::getFixedStack(), + SPFI, SlotVT); } // Result is a load from the stack slot. @@ -4776,9 +4793,15 @@ SDOperand SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) { // Create a vector sized/aligned stack slot, store the value to element #0, // then load the whole vector back out. SDOperand StackPtr = DAG.CreateStackTemporary(Node->getValueType(0)); + + FrameIndexSDNode *StackPtrFI = dyn_cast<FrameIndexSDNode>(StackPtr); + assert(StackPtrFI); + int SPFI = StackPtrFI->getIndex(); + SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Node->getOperand(0), StackPtr, - NULL, 0); - return DAG.getLoad(Node->getValueType(0), Ch, StackPtr, NULL, 0); + &PseudoSourceValue::getFixedStack(), SPFI); + return DAG.getLoad(Node->getValueType(0), Ch, StackPtr, + &PseudoSourceValue::getFixedStack(), SPFI); } @@ -4842,7 +4865,8 @@ SDOperand SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) { } Constant *CP = ConstantVector::get(CV); SDOperand CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy()); - return DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, NULL, 0); + return DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, + &PseudoSourceValue::getConstantPool(), 0); } if (SplatValue.Val) { // Splat of one value? @@ -5184,11 +5208,14 @@ ExpandIntToFP(bool isSigned, MVT::ValueType DestTy, SDOperand Source) { CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset); SDOperand FudgeInReg; if (DestTy == MVT::f32) - FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx, NULL, 0); + FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx, + &PseudoSourceValue::getConstantPool(), 0); else if (MVT::getSizeInBits(DestTy) > MVT::getSizeInBits(MVT::f32)) // FIXME: Avoid the extend by construction the right constantpool? FudgeInReg = DAG.getExtLoad(ISD::EXTLOAD, DestTy, DAG.getEntryNode(), - CPIdx, NULL, 0, MVT::f32); + CPIdx, + &PseudoSourceValue::getConstantPool(), 0, + MVT::f32); else assert(0 && "Unexpected conversion"); @@ -5330,11 +5357,14 @@ SDOperand SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned, CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset); SDOperand FudgeInReg; if (DestVT == MVT::f32) - FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx, NULL, 0); + FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx, + &PseudoSourceValue::getConstantPool(), 0); else { - FudgeInReg = LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, DestVT, - DAG.getEntryNode(), CPIdx, - NULL, 0, MVT::f32)); + FudgeInReg = + LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, DestVT, + DAG.getEntryNode(), CPIdx, + &PseudoSourceValue::getConstantPool(), 0, + MVT::f32)); } return DAG.getNode(ISD::FADD, DestVT, Tmp1, FudgeInReg); @@ -6743,10 +6773,16 @@ void SelectionDAGLegalize::SplitVectorOp(SDOperand Op, SDOperand &Lo, // Lower to a store/load so that it can be split. // FIXME: this could be improved probably. SDOperand Ptr = DAG.CreateStackTemporary(InOp.getValueType()); + FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Ptr.Val); + assert(FI && "Expecting CreateStackTemporary to return a frame index.\n"); SDOperand St = DAG.getStore(DAG.getEntryNode(), - InOp, Ptr, NULL, 0); - InOp = DAG.getLoad(Op.getValueType(), St, Ptr, NULL, 0); + InOp, Ptr, + &PseudoSourceValue::getFixedStack(), + FI->getIndex()); + InOp = DAG.getLoad(Op.getValueType(), St, Ptr, + &PseudoSourceValue::getFixedStack(), + FI->getIndex()); } // Split the vector and convert each of the pieces now. SplitVectorOp(InOp, Lo, Hi); diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp index a165b17dff..043f7c1cb2 100644 --- a/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp +++ b/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp @@ -277,15 +277,27 @@ unsigned ScheduleDAG::CountResults(SDNode *Node) { return N; } -/// CountOperands The inputs to target nodes have any actual inputs first, -/// followed by an optional chain operand, then flag operands. Compute the -/// number of actual operands that will go into the machine instr. +/// CountOperands - The inputs to target nodes have any actual inputs first, +/// followed by optional memory operands chain operand, then flag operands. +/// Compute the number of actual operands that will go into the machine istr. unsigned ScheduleDAG::CountOperands(SDNode *Node) { unsigned N = Node->getNumOperands(); while (N && Node->getOperand(N - 1).getValueType() == MVT::Flag) --N; if (N && Node->getOperand(N - 1).getValueType() == MVT::Other) --N; // Ignore chain if it exists. + while (N && MemOperandSDNode::classof(Node->getOperand(N - 1).Val)) + --N; // Ignore MemOperand nodes + return N; +} + +/// CountMemOperands - Find the index of the last MemOperandSDNode operand +unsigned ScheduleDAG::CountMemOperands(SDNode *Node) { + unsigned N = Node->getNumOperands(); + while (N && Node->getOperand(N - 1).getValueType() == MVT::Flag) + --N; + if (N && Node->getOperand(N - 1).getValueType() == MVT::Other) + --N; // Ignore chain if it exists. return N; } @@ -517,6 +529,10 @@ void ScheduleDAG::AddOperand(MachineInstr *MI, SDOperand Op, } +void ScheduleDAG::AddMemOperand(MachineInstr *MI, const MemOperand &MO) { + MI->addMemOperand(MO); +} + // Returns the Register Class of a subregister static const TargetRegisterClass *getSubRegisterRegClass( const TargetRegisterClass *TRC, @@ -675,6 +691,7 @@ void ScheduleDAG::EmitNode(SDNode *Node, unsigned InstanceNo, unsigned NumResults = CountResults(Node); unsigned NodeOperands = CountOperands(Node); + unsigned NodeMemOperands = CountMemOperands(Node); unsigned NumMIOperands = NodeOperands + NumResults; bool HasPhysRegOuts = (NumResults > II.getNumDefs()) && II.getImplicitDefs() != 0; @@ -697,6 +714,10 @@ void ScheduleDAG::EmitNode(SDNode *Node, unsigned InstanceNo, for (unsigned i = 0; i != NodeOperands; ++i) AddOperand(MI, Node->getOperand(i), i+II.getNumDefs(), &II, VRBaseMap); + // Emit all of the memory operands of this instruction + for (unsigned i = NodeOperands; i != NodeMemOperands; ++i) + AddMemOperand(MI, cast<MemOperandSDNode>(Node->getOperand(i))->MO); + // Commute node if it has been determined to be profitable. if (CommuteSet.count(Node)) { MachineInstr *NewMI = TII->commuteInstruction(MI); @@ -737,6 +758,7 @@ void ScheduleDAG::EmitNode(SDNode *Node, unsigned InstanceNo, case ISD::TokenFactor: case ISD::LABEL: case ISD::DECLARE: + case ISD::SRCVALUE: break; case ISD::CopyToReg: { unsigned InReg; diff --git a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp index 4b68fb7e95..71c6b5589f 100644 --- a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp +++ b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp @@ -21,6 +21,7 @@ #include "llvm/CodeGen/MachineConstantPool.h" #include "llvm/CodeGen/MachineFrameInfo.h" #include "llvm/CodeGen/MachineModuleInfo.h" +#include "llvm/CodeGen/PseudoSourceValue.h" #include "llvm/Support/MathExtras.h" #include "llvm/Target/MRegisterInfo.h" #include "llvm/Target/TargetData.h" @@ -361,10 +362,16 @@ static void AddNodeIDNode(FoldingSetNodeID &ID, SDNode *N) { case ISD::Register: ID.AddInteger(cast<RegisterSDNode>(N)->getReg()); break; - case ISD::SRCVALUE: { - SrcValueSDNode *SV = cast<SrcValueSDNode>(N); - ID.AddPointer(SV->getValue()); - ID.AddInteger(SV->getOffset()); + case ISD::SRCVALUE: + ID.AddPointer(cast<SrcValueSDNode>(N)->getValue()); + break; + case ISD::MEMOPERAND: { + const MemOperand &MO = cast<MemOperandSDNode>(N)->MO; + ID.AddPointer(MO.getValue()); + ID.AddInteger(MO.getFlags()); + ID.AddInteger(MO.getOffset()); + ID.AddInteger(MO.getSize()); + ID.AddInteger(MO.getAlignment()); break; } case ISD::FrameIndex: @@ -937,18 +944,42 @@ SDOperand SelectionDAG::getRegister(unsigned RegNo, MVT::ValueType VT) { return SDOperand(N, 0); } -SDOperand SelectionDAG::getSrcValue(const Value *V, int Offset) { +SDOperand SelectionDAG::getSrcValue(const Value *V) { assert((!V || isa<PointerType>(V->getType())) && "SrcValue is not a pointer?"); FoldingSetNodeID ID; AddNodeIDNode(ID, ISD::SRCVALUE, getVTList(MVT::Other), 0, 0); ID.AddPointer(V); - ID.AddInteger(Offset); + void *IP = 0; if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) return SDOperand(E, 0); - SDNode *N = new SrcValueSDNode(V, Offset); + + SDNode *N = new SrcValueSDNode(V); + CSEMap.InsertNode(N, IP); + AllNodes.push_back(N); + return SDOperand(N, 0); +} + +SDOperand SelectionDAG::getMemOperand(const MemOperand &MO) { + const Value *v = MO.getValue(); + assert((!v || isa<PointerType>(v->getType())) && + "SrcValue is not a pointer?"); + + FoldingSetNodeID ID; + AddNodeIDNode(ID, ISD::MEMOPERAND, getVTList(MVT::Other), 0, 0); + ID.AddPointer(v); + ID.AddInteger(MO.getFlags()); + ID.AddInteger(MO.getOffset()); + ID.AddInteger(MO.getSize()); + ID.AddInteger(MO.getAlignment()); + + void *IP = 0; + if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) + return SDOperand(E, 0); + + SDNode *N = new MemOperandSDNode(MO); CSEMap.InsertNode(N, IP); AllNodes.push_back(N); return SDOperand(N, 0); @@ -3479,6 +3510,7 @@ void JumpTableSDNode::ANCHOR() {} void ConstantPoolSDNode::ANCHOR() {} void BasicBlockSDNode::ANCHOR() {} void SrcValueSDNode::ANCHOR() {} +void MemOperandSDNode::ANCHOR() {} void RegisterSDNode::ANCHOR() {} void ExternalSymbolSDNode::ANCHOR() {} void CondCodeSDNode::ANCHOR() {} @@ -3503,6 +3535,26 @@ GlobalAddressSDNode::GlobalAddressSDNode(bool isTarget, const GlobalValue *GA, TheGlobal = const_cast<GlobalValue*>(GA); } +/// getMemOperand - Return a MemOperand object describing the memory +/// reference performed by this load or store. +MemOperand LSBaseSDNode::getMemOperand() const { + int Size = (MVT::getSizeInBits(getMemoryVT()) + 7) >> 3; + int Flags = + getOpcode() == ISD::LOAD ? MemOperand::MOLoad : MemOperand::MOStore; + if (IsVolatile) Flags |= MemOperand::MOVolatile; + + // Check if the load references a frame index, and does not have + // an SV attached. + const FrameIndexSDNode *FI = + dyn_cast<const FrameIndexSDNode>(getBasePtr().Val); + if (!getSrcValue() && FI) + return MemOperand(&PseudoSourceValue::getFixedStack(), Flags, + FI->getIndex(), Size, Alignment); + else + return MemOperand(getSrcValue(), Flags, + getSrcValueOffset(), Size, Alignment); +} + /// Profile - Gather unique data for the node. /// void SDNode::Profile(FoldingSetNodeID &ID) { @@ -3695,6 +3747,7 @@ std::string SDNode::getOperationName(const SelectionDAG *G) const { case ISD::PCMARKER: return "PCMarker"; case ISD::READCYCLECOUNTER: return "ReadCycleCounter"; case ISD::SRCVALUE: return "SrcValue"; + case ISD::MEMOPERAND: return "MemOperand"; case ISD::EntryToken: return "EntryToken"; case ISD::TokenFactor: return "TokenFactor"; case ISD::AssertSext: return "AssertSext"; @@ -4000,9 +4053,14 @@ void SDNode::dump(const SelectionDAG *G) const { cerr << "'" << ES->getSymbol() << "'"; } else if (const SrcValueSDNode *M = dyn_cast<SrcValueSDNode>(this)) { if (M->getValue()) - cerr << "<" << M->getValue() << ":" << M->getOffset() << ">"; + cerr << "<" << M->getValue() << ">"; + else + cerr << "<null>"; + } else if (const MemOperandSDNode *M = dyn_cast<MemOperandSDNode>(this)) { + if (M->MO.getValue()) + cerr << "<" << M->MO.getValue() << ":" << M->MO.getOffset() << ">"; else - cerr << "<null:" << M->getOffset() << ">"; + cerr << "<null:" << M->MO.getOffset() << ">"; } else if (const VTSDNode *N = dyn_cast<VTSDNode>(this)) { cerr << ":" << MVT::getValueTypeString(N->getVT()); } else if (const LoadSDNode *LD = dyn_cast<LoadSDNode>(this)) { diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp index 95c791b43e..719b949591 100644 --- a/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp +++ b/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp @@ -142,9 +142,14 @@ std::string DOTGraphTraits<SelectionDAG*>::getNodeLabel(const SDNode *Node, Op += "'" + std::string(ES->getSymbol()) + "'"; } else if (const SrcValueSDNode *M = dyn_cast<SrcValueSDNode>(Node)) { if (M->getValue()) - Op += "<" + M->getValue()->getName() + ":" + itostr(M->getOffset()) + ">"; + Op += "<" + M->getValue()->getName() + ">"; else - Op += "<null:" + itostr(M->getOffset()) + ">"; + Op += "<null>"; + } else if (const MemOperandSDNode *M = dyn_cast<MemOperandSDNode>(Node)) { + if (M->MO.getValue()) + Op += "<" + M->MO.getValue()->getName() + ":" + itostr(M->MO.getOffset()) + ">"; + else + Op += "<null:" + itostr(M->MO.getOffset()) + ">"; } else if (const VTSDNode *N = dyn_cast<VTSDNode>(Node)) { Op = Op + " VT=" + MVT::getValueTypeString(N->getVT()); } else if (const StringSDNode *N = dyn_cast<StringSDNode>(Node)) { diff --git a/lib/Target/ARM/ARMISelLowering.cpp b/lib/Target/ARM/ARMISelLowering.cpp index 02f53cc59a..8176f24ef3 100644 --- a/lib/Target/ARM/ARMISelLowering.cpp +++ b/lib/Target/ARM/ARMISelLowering.cpp @@ -905,9 +905,8 @@ static SDOperand LowerVASTART(SDOperand Op, SelectionDAG &DAG, // memory location argument. MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT); - SrcValueSDNode *SV = cast<SrcValueSDNode>(Op.getOperand(2)); - return DAG.getStore(Op.getOperand(0), FR, Op.getOperand(1), SV->getValue(), - SV->getOffset()); + const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); + return DAG.getStore(Op.getOperand(0), FR, Op.getOperand(1), SV, 0); } static SDOperand LowerFORMAL_ARGUMENT(SDOperand Op, SelectionDAG &DAG, diff --git a/lib/Target/Alpha/AlphaISelLowering.cpp b/lib/Target/Alpha/AlphaISelLowering.cpp index c359a5bcdb..d20e1f7fb1 100644 --- a/lib/Target/Alpha/AlphaISelLowering.cpp +++ b/lib/Target/Alpha/AlphaISelLowering.cpp @@ -491,10 +491,9 @@ SDOperand AlphaTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) { case ISD::VAARG: { SDOperand Chain = Op.getOperand(0); SDOperand VAListP = Op.getOperand(1); - SrcValueSDNode *VAListS = cast<SrcValueSDNode>(Op.getOperand(2)); + const Value *VAListS = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); - SDOperand Base = DAG.getLoad(MVT::i64, Chain, VAListP, VAListS->getValue(), - VAListS->getOffset()); + SDOperand Base = DAG.getLoad(MVT::i64, Chain, VAListP, VAListS, 0); SDOperand Tmp = DAG.getNode(ISD::ADD, MVT::i64, VAListP, DAG.getConstant(8, MVT::i64)); SDOperand Offset = DAG.getExtLoad(ISD::SEXTLOAD, MVT::i64, Base.getValue(1), @@ -527,13 +526,11 @@ SDOperand AlphaTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) { SDOperand Chain = Op.getOperand(0); SDOperand DestP = Op.getOperand(1); SDOperand SrcP = Op.getOperand(2); - SrcValueSDNode *DestS = cast<SrcValueSDNode>(Op.getOperand(3)); - SrcValueSDNode *SrcS = cast<SrcValueSDNode>(Op.getOperand(4)); + const Value *DestS = cast<SrcValueSDNode>(Op.getOperand(3))->getValue(); + const Value *SrcS = cast<SrcValueSDNode>(Op.getOperand(4))->getValue(); - SDOperand Val = DAG.getLoad(getPointerTy(), Chain, SrcP, - SrcS->getValue(), SrcS->getOffset()); - SDOperand Result = DAG.getStore(Val.getValue(1), Val, DestP, DestS->getValue(), - DestS->getOffset()); + SDOperand Val = DAG.getLoad(getPointerTy(), Chain, SrcP, SrcS, 0); + SDOperand Result = DAG.getStore(Val.getValue(1), Val, DestP, DestS, 0); SDOperand NP = DAG.getNode(ISD::ADD, MVT::i64, SrcP, DAG.getConstant(8, MVT::i64)); Val = DAG.getExtLoad(ISD::SEXTLOAD, MVT::i64, Result, NP, NULL,0, MVT::i32); @@ -544,12 +541,11 @@ SDOperand AlphaTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) { case ISD::VASTART: { SDOperand Chain = Op.getOperand(0); SDOperand VAListP = Op.getOperand(1); - SrcValueSDNode *VAListS = cast<SrcValueSDNode>(Op.getOperand(2)); + const Value *VAListS = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); // vastart stores the address of the VarArgsBase and VarArgsOffset SDOperand FR = DAG.getFrameIndex(VarArgsBase, MVT::i64); - SDOperand S1 = DAG.getStore(Chain, FR, VAListP, VAListS->getValue(), - VAListS->getOffset()); + SDOperand S1 = DAG.getStore(Chain, FR, VAListP, VAListS, 0); SDOperand SA2 = DAG.getNode(ISD::ADD, MVT::i64, VAListP, DAG.getConstant(8, MVT::i64)); return DAG.getTruncStore(S1, DAG.getConstant(VarArgsOffset, MVT::i64), diff --git a/lib/Target/IA64/IA64ISelLowering.cpp b/lib/Target/IA64/IA64ISelLowering.cpp index d81d5e6686..ef772749ed 100644 --- a/lib/Target/IA64/IA64ISelLowering.cpp +++ b/lib/Target/IA64/IA64ISelLowering.cpp @@ -581,16 +581,16 @@ LowerOperation(SDOperand Op, SelectionDAG &DAG) { } case ISD::VAARG: { MVT::ValueType VT = getPointerTy(); - SrcValueSDNode *SV = cast<SrcValueSDNode>(Op.getOperand(2)); + const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); SDOperand VAList = DAG.getLoad(VT, Op.getOperand(0), Op.getOperand(1), - SV->getValue(), SV->getOffset()); + SV, 0); // Increment the pointer, VAList, to the next vaarg SDOperand VAIncr = DAG.getNode(ISD::ADD, VT, VAList, DAG.getConstant(MVT::getSizeInBits(VT)/8, VT)); // Store the incremented VAList to the legalized pointer VAIncr = DAG.getStore(VAList.getValue(1), VAIncr, - Op.getOperand(1), SV->getValue(), SV->getOffset()); + Op.getOperand(1), SV, 0); // Load the actual argument out of the pointer VAList return DAG.getLoad(Op.getValueType(), VAIncr, VAList, NULL, 0); } @@ -598,9 +598,8 @@ LowerOperation(SDOperand Op, SelectionDAG &DAG) { // vastart just stores the address of the VarArgsFrameIndex slot into the // memory location argument. SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, MVT::i64); - SrcValueSDNode *SV = cast<SrcValueSDNode>(Op.getOperand(2)); - return DAG.getStore(Op.getOperand(0), FR, - Op.getOperand(1), SV->getValue(), SV->getOffset()); + const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); + return DAG.getStore(Op.getOperand(0), FR, Op.getOperand(1), SV, 0); } // Frame & Return address. Currently unimplemented case ISD::RETURNADDR: break; diff --git a/lib/Target/PowerPC/PPCISelLowering.cpp b/lib/Target/PowerPC/PPCISelLowering.cpp index e17f82d6aa..28aa35c737 100644 --- a/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/lib/Target/PowerPC/PPCISelLowering.cpp @@ -24,6 +24,7 @@ #include "llvm/CodeGen/MachineFunction.h" #include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/CodeGen/MachineRegisterInfo.h" +#include "llvm/CodeGen/PseudoSourceValue.h" #include "llvm/CodeGen/SelectionDAG.h" #include "llvm/Constants.h" #include "llvm/Function.h" @@ -1175,9 +1176,8 @@ static SDOperand LowerVASTART(SDOperand Op, SelectionDAG &DAG, // memory location argument. MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT); - SrcValueSDNode *SV = cast<SrcValueSDNode>(Op.getOperand(2)); - return DAG.getStore(Op.getOperand(0), FR, Op.getOperand(1), SV->getValue(), - SV->getOffset()); + const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); + return DAG.getStore(Op.getOperand(0), FR, Op.getOperand(1), SV, 0); } // For ELF 32 ABI we follow the layout of the va_list struct. @@ -1211,37 +1211,41 @@ static SDOperand LowerVASTART(SDOperand Op, SelectionDAG &DAG, MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); - SDOperand StackOffset = DAG.getFrameIndex(VarArgsStackOffset, PtrVT); + SDOperand StackOffsetFI = DAG.getFrameIndex(VarArgsStackOffset, PtrVT); SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT); - SDOperand ConstFrameOffset = DAG.getConstant(MVT::getSizeInBits(PtrVT)/8, - PtrVT); - SDOperand ConstStackOffset = DAG.getConstant(MVT::getSizeInBits(PtrVT)/8 - 1, - PtrVT); - SDOperand ConstFPROffset = DAG.getConstant(1, PtrVT); + uint64_t FrameOffset = MVT::getSizeInBits(PtrVT)/8; + SDOperand ConstFrameOffset = DAG.getConstant(FrameOffset, PtrVT); + + uint64_t StackOffset = MVT::getSizeInBits(PtrVT)/8 - 1; + SDOperand ConstStackOffset = DAG.getConstant(StackOffset, PtrVT); + + uint64_t FPROffset = 1; + SDOperand ConstFPROffset = DAG.getConstant(FPROffset, PtrVT); - SrcValueSDNode *SV = cast<SrcValueSDNode>(Op.getOperand(2)); + const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); // Store first byte : number of int regs SDOperand firstStore = DAG.getStore(Op.getOperand(0), ArgGPR, - Op.getOperand(1), SV->getValue(), - SV->getOffset()); + Op.getOperand(1), SV, 0); + uint64_t nextOffset = FPROffset; SDOperand nextPtr = DAG.getNode(ISD::ADD, PtrVT, Op.getOperand(1), ConstFPROffset); // Store second byte : number of float regs - SDOperand secondStore = DAG.getStore(firstStore, ArgFPR, nextPtr, - SV->getValue(), SV->getOffset()); + SDOperand secondStore = |