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| author | Matt Beaumont-Gay <matthewbg@google.com> | 2010-12-07 23:26:21 +0000 |
|---|---|---|
| committer | Matt Beaumont-Gay <matthewbg@google.com> | 2010-12-07 23:26:21 +0000 |
| commit | 2bf315f0871a65061d8fd9c867587cfe02adefc7 (patch) | |
| tree | 160bf29e14849653a711167d9464d0a75a8fd8ca /lib | |
| parent | fe58f95f3604b394916bee7bd289e1f0e0488ec5 (diff) | |
Fix a warning about a variable which is only used in an assertion.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121206 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
| -rw-r--r-- | lib/Target/ARM/ARMMCCodeEmitter.cpp | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/lib/Target/ARM/ARMMCCodeEmitter.cpp b/lib/Target/ARM/ARMMCCodeEmitter.cpp index 0376a16e4b..229e00e65d 100644 --- a/lib/Target/ARM/ARMMCCodeEmitter.cpp +++ b/lib/Target/ARM/ARMMCCodeEmitter.cpp @@ -667,9 +667,9 @@ getAddrModeThumbSPOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups) const { // [SP, #imm] // {7-0} = imm8 - const MCOperand &MO = MI.getOperand(OpIdx); const MCOperand &MO1 = MI.getOperand(OpIdx + 1); - assert (MO.getReg() == ARM::SP && "Unexpected base register!"); + assert (MI.getOperand(OpIdx).getReg() == ARM::SP && + "Unexpected base register!"); // The immediate is already shifted for the implicit zeroes, so no change // here. return MO1.getImm() & 0xff; |