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authorBrian Gaeke <gaeke@uiuc.edu>2004-04-19 19:12:12 +0000
committerBrian Gaeke <gaeke@uiuc.edu>2004-04-19 19:12:12 +0000
commit0eb61037f7f554f705a511b47a6cf43f0b39bb9a (patch)
treef6770c2a377b5860bd5b5971466257c750cf7bf3 /lib
parent9a459abed2ecd06b5b5d2f517b27cd9bf1919690 (diff)
Make it legal to request a load or store of %fsr.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@13073 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
-rw-r--r--lib/Target/SparcV9/SparcV9RegInfo.cpp2
1 files changed, 2 insertions, 0 deletions
diff --git a/lib/Target/SparcV9/SparcV9RegInfo.cpp b/lib/Target/SparcV9/SparcV9RegInfo.cpp
index b6da2e6403..0f598485bf 100644
--- a/lib/Target/SparcV9/SparcV9RegInfo.cpp
+++ b/lib/Target/SparcV9/SparcV9RegInfo.cpp
@@ -808,6 +808,7 @@ SparcV9RegInfo::cpReg2MemMI(std::vector<MachineInstr*>& mvec,
cpReg2MemMI(mvec, scratchReg, PtrReg, Offset, IntRegType);
return;
+ case SpecialRegType: // used only for %fsr itself.
case FloatCCRegType: {
unsigned fsrReg = getUnifiedRegNum(SparcV9RegInfo::SpecialRegClassID,
SparcV9SpecialRegClass::fsr);
@@ -898,6 +899,7 @@ SparcV9RegInfo::cpMem2RegMI(std::vector<MachineInstr*>& mvec,
SparcV9IntCCRegClass::ccr), MachineOperand::Def));
break;
+ case SpecialRegType: // used only for %fsr itself
case FloatCCRegType: {
unsigned fsrRegNum = getUnifiedRegNum(SparcV9RegInfo::SpecialRegClassID,
SparcV9SpecialRegClass::fsr);