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authorChris Lattner <sabre@nondot.org>2011-02-06 21:44:57 +0000
committerChris Lattner <sabre@nondot.org>2011-02-06 21:44:57 +0000
commit35bda8914c0d1c02a6f90f42e7810c83150737e1 (patch)
treeb210ccd009a7ac5331c76c6393b5b45d141d12d0 /lib/VMCore/AsmWriter.cpp
parentbd75021465e7f8c81785e692cfd3ce559764e46f (diff)
enhance vmcore to know that udiv's can be exact, and add a trivial
instcombine xform to exercise this. Nothing forms exact udivs yet though. This is progress on PR8862 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124992 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/VMCore/AsmWriter.cpp')
-rw-r--r--lib/VMCore/AsmWriter.cpp3
1 files changed, 2 insertions, 1 deletions
diff --git a/lib/VMCore/AsmWriter.cpp b/lib/VMCore/AsmWriter.cpp
index 1a11d9c798..5b56cb572c 100644
--- a/lib/VMCore/AsmWriter.cpp
+++ b/lib/VMCore/AsmWriter.cpp
@@ -831,7 +831,8 @@ static void WriteOptimizationInfo(raw_ostream &Out, const User *U) {
Out << " nuw";
if (OBO->hasNoSignedWrap())
Out << " nsw";
- } else if (const SDivOperator *Div = dyn_cast<SDivOperator>(U)) {
+ } else if (const PossiblyExactOperator *Div =
+ dyn_cast<PossiblyExactOperator>(U)) {
if (Div->isExact())
Out << " exact";
} else if (const GEPOperator *GEP = dyn_cast<GEPOperator>(U)) {