Simplify some logic in ComputeMaskedBits. And change ComputeMaskedBits

to pass the mask APInt by value, not by reference. 


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47096 91177308-0d34-0410-b5e6-96231b3b80d8

9 files changed, 10 insertions, 10 deletions

diff --git a/lib/Target/ARM/ARMISelLowering.cpp b/lib/Target/ARM/ARMISelLowering.cpp
index a6c669dc88..a4ab393812 100644
--- a/lib/Target/ARM/ARMISelLowering.cpp
+++ b/lib/Target/ARM/ARMISelLowering.cpp
@@ -1762,7 +1762,7 @@ bool ARMTargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op,
 }
 
 void ARMTargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op,
-                                                       APInt Mask,
+                                                       const APInt &Mask,
                                                        APInt &KnownZero, 
                                                        APInt &KnownOne,
                                                        const SelectionDAG &DAG,
diff --git a/lib/Target/ARM/ARMISelLowering.h b/lib/Target/ARM/ARMISelLowering.h
index 80ee51a164..285a20d23f 100644
--- a/lib/Target/ARM/ARMISelLowering.h
+++ b/lib/Target/ARM/ARMISelLowering.h
@@ -106,7 +106,7 @@ namespace llvm {
                                             SelectionDAG &DAG);
 
     virtual void computeMaskedBitsForTargetNode(const SDOperand Op,
-                                                APInt Mask,
+                                                const APInt &Mask,
                                                 APInt &KnownZero, 
                                                 APInt &KnownOne,
                                                 const SelectionDAG &DAG,
diff --git a/lib/Target/CellSPU/SPUISelLowering.cpp b/lib/Target/CellSPU/SPUISelLowering.cpp
index 6fe6e48bc8..f6e33599c6 100644
--- a/lib/Target/CellSPU/SPUISelLowering.cpp
+++ b/lib/Target/CellSPU/SPUISelLowering.cpp
@@ -2668,7 +2668,7 @@ SPUTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
 
 void
 SPUTargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op,
-                                                  APInt Mask,
+                                                  const APInt &Mask,
                                                   APInt &KnownZero, 
                                                   APInt &KnownOne,
                                                   const SelectionDAG &DAG,
diff --git a/lib/Target/CellSPU/SPUISelLowering.h b/lib/Target/CellSPU/SPUISelLowering.h
index 3abb9d17fa..29242df71b 100644
--- a/lib/Target/CellSPU/SPUISelLowering.h
+++ b/lib/Target/CellSPU/SPUISelLowering.h
@@ -108,7 +108,7 @@ namespace llvm {
     virtual SDOperand PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
 
     virtual void computeMaskedBitsForTargetNode(const SDOperand Op,
-                                                APInt Mask,
+                                                const APInt &Mask,
                                                 APInt &KnownZero, 
                                                 APInt &KnownOne,
                                                 const SelectionDAG &DAG,
diff --git a/lib/Target/PowerPC/PPCISelLowering.cpp b/lib/Target/PowerPC/PPCISelLowering.cpp
index 6c4468c359..53be370f0a 100644
--- a/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -3451,7 +3451,7 @@ SDOperand PPCTargetLowering::PerformDAGCombine(SDNode *N,
 //===----------------------------------------------------------------------===//
 
 void PPCTargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op,
-                                                       APInt Mask,
+                                                       const APInt &Mask,
                                                        APInt &KnownZero, 
                                                        APInt &KnownOne,
                                                        const SelectionDAG &DAG,
diff --git a/lib/Target/PowerPC/PPCISelLowering.h b/lib/Target/PowerPC/PPCISelLowering.h
index 2b20e26c16..3843998b50 100644
--- a/lib/Target/PowerPC/PPCISelLowering.h
+++ b/lib/Target/PowerPC/PPCISelLowering.h
@@ -254,7 +254,7 @@ namespace llvm {
     virtual SDOperand PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
     
     virtual void computeMaskedBitsForTargetNode(const SDOperand Op,
-                                                APInt Mask,
+                                                const APInt &Mask,
                                                 APInt &KnownZero, 
                                                 APInt &KnownOne,
                                                 const SelectionDAG &DAG,
diff --git a/lib/Target/Sparc/SparcISelDAGToDAG.cpp b/lib/Target/Sparc/SparcISelDAGToDAG.cpp
index 81e15397c7..29fe6a4160 100644
--- a/lib/Target/Sparc/SparcISelDAGToDAG.cpp
+++ b/lib/Target/Sparc/SparcISelDAGToDAG.cpp
@@ -110,7 +110,7 @@ namespace {
     /// in Mask are known to be either zero or one and return them in the 
     /// KnownZero/KnownOne bitsets.
     virtual void computeMaskedBitsForTargetNode(const SDOperand Op,
-                                                APInt Mask,
+                                                const APInt &Mask,
                                                 APInt &KnownZero, 
                                                 APInt &KnownOne,
                                                 const SelectionDAG &DAG,
@@ -270,7 +270,7 @@ const char *SparcTargetLowering::getTargetNodeName(unsigned Opcode) const {
 /// be zero. Op is expected to be a target specific node. Used by DAG
 /// combiner.
 void SparcTargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op,
-                                                         APInt Mask,
+                                                         const APInt &Mask,
                                                          APInt &KnownZero, 
                                                          APInt &KnownOne,
                                                          const SelectionDAG &DAG,
diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp
index c7e055dbbd..556aaac9ea 100644
--- a/lib/Target/X86/X86ISelLowering.cpp
+++ b/lib/Target/X86/X86ISelLowering.cpp
@@ -5640,7 +5640,7 @@ X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
 //===----------------------------------------------------------------------===//
 
 void X86TargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op,
-                                                       APInt Mask,
+                                                       const APInt &Mask,
                                                        APInt &KnownZero,
                                                        APInt &KnownOne,
                                                        const SelectionDAG &DAG,
diff --git a/lib/Target/X86/X86ISelLowering.h b/lib/Target/X86/X86ISelLowering.h
index e4ca85068a..b191dfac33 100644
--- a/lib/Target/X86/X86ISelLowering.h
+++ b/lib/Target/X86/X86ISelLowering.h
@@ -379,7 +379,7 @@ namespace llvm {
     /// in Mask are known to be either zero or one and return them in the 
     /// KnownZero/KnownOne bitsets.
     virtual void computeMaskedBitsForTargetNode(const SDOperand Op,
-                                                APInt Mask,
+                                                const APInt &Mask,
                                                 APInt &KnownZero, 
                                                 APInt &KnownOne,
                                                 const SelectionDAG &DAG,