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| author | Rafael Espindola <rafael.espindola@gmail.com> | 2006-09-04 19:05:01 +0000 |
|---|---|---|
| committer | Rafael Espindola <rafael.espindola@gmail.com> | 2006-09-04 19:05:01 +0000 |
| commit | 3a02f020eb72cb10f7f794532ddc35e478f7e86b (patch) | |
| tree | ede56c8859e74e025fe3d6e350008b5e45f915c8 /lib/Target | |
| parent | 2130b99eb29796d80b978f7c4b4f64dcca0d1309 (diff) | |
add support for returning 64bit values
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30103 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target')
| -rw-r--r-- | lib/Target/ARM/ARMISelDAGToDAG.cpp | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/lib/Target/ARM/ARMISelDAGToDAG.cpp b/lib/Target/ARM/ARMISelDAGToDAG.cpp index eba7c78aaa..9a19497574 100644 --- a/lib/Target/ARM/ARMISelDAGToDAG.cpp +++ b/lib/Target/ARM/ARMISelDAGToDAG.cpp @@ -238,6 +238,15 @@ static SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG) { if (DAG.getMachineFunction().liveout_empty()) DAG.getMachineFunction().addLiveOut(ARM::R0); break; + case 5: + Copy = DAG.getCopyToReg(Chain, ARM::R1, Op.getOperand(3), SDOperand()); + Copy = DAG.getCopyToReg(Copy, ARM::R0, Op.getOperand(1), Copy.getValue(1)); + // If we haven't noted the R0+R1 are live out, do so now. + if (DAG.getMachineFunction().liveout_empty()) { + DAG.getMachineFunction().addLiveOut(ARM::R0); + DAG.getMachineFunction().addLiveOut(ARM::R1); + } + break; } //We must use RET_FLAG instead of BRIND because BRIND doesn't have a flag |