diff options
| author | Richard Osborne <richard@xmos.com> | 2013-01-20 17:22:43 +0000 |
|---|---|---|
| committer | Richard Osborne <richard@xmos.com> | 2013-01-20 17:22:43 +0000 |
| commit | a68c64fbb2f1bee7f9313f3ee19c35677563f974 (patch) | |
| tree | 69ebec49ff5874d9c22c4a54f8cc7cbd4770a5c4 /lib/Target/XCore/Disassembler/XCoreDisassembler.cpp | |
| parent | 62b8786d12ceacafd665d4a1fbb6e90af0ec368c (diff) | |
Add instruction encodings / disassembler support for 2rus instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172985 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/XCore/Disassembler/XCoreDisassembler.cpp')
| -rw-r--r-- | lib/Target/XCore/Disassembler/XCoreDisassembler.cpp | 57 |
1 files changed, 57 insertions, 0 deletions
diff --git a/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp b/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp index baa9566490..3e0a16f885 100644 --- a/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp +++ b/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp @@ -137,6 +137,16 @@ static DecodeStatus Decode3RInstruction(MCInst &Inst, uint64_t Address, const void *Decoder); +static DecodeStatus Decode2RUSInstruction(MCInst &Inst, + unsigned Insn, + uint64_t Address, + const void *Decoder); + +static DecodeStatus Decode2RUSBitpInstruction(MCInst &Inst, + unsigned Insn, + uint64_t Address, + const void *Decoder); + #include "XCoreGenDisassemblerTables.inc" static DecodeStatus DecodeGRRegsRegisterClass(MCInst &Inst, @@ -202,6 +212,12 @@ Decode2OpInstructionFail(MCInst &Inst, unsigned Insn, uint64_t Address, // Try and decode as a 3R instruction. unsigned Opcode = fieldFromInstruction(Insn, 11, 5); switch (Opcode) { + case 0x0: + Inst.setOpcode(XCore::STW_2rus); + return Decode2RUSInstruction(Inst, Insn, Address, Decoder); + case 0x1: + Inst.setOpcode(XCore::LDW_2rus); + return Decode2RUSInstruction(Inst, Insn, Address, Decoder); case 0x2: Inst.setOpcode(XCore::ADD_3r); return Decode3RInstruction(Inst, Insn, Address, Decoder); @@ -232,6 +248,21 @@ Decode2OpInstructionFail(MCInst &Inst, unsigned Insn, uint64_t Address, case 0x11: Inst.setOpcode(XCore::LD8U_3r); return Decode3RInstruction(Inst, Insn, Address, Decoder); + case 0x12: + Inst.setOpcode(XCore::ADD_2rus); + return Decode2RUSInstruction(Inst, Insn, Address, Decoder); + case 0x13: + Inst.setOpcode(XCore::SUB_2rus); + return Decode2RUSInstruction(Inst, Insn, Address, Decoder); + case 0x14: + Inst.setOpcode(XCore::SHL_2rus); + return Decode2RUSBitpInstruction(Inst, Insn, Address, Decoder); + case 0x15: + Inst.setOpcode(XCore::SHR_2rus); + return Decode2RUSBitpInstruction(Inst, Insn, Address, Decoder); + case 0x16: + Inst.setOpcode(XCore::EQ_2rus); + return Decode2RUSInstruction(Inst, Insn, Address, Decoder); case 0x18: Inst.setOpcode(XCore::LSS_3r); return Decode3RInstruction(Inst, Insn, Address, Decoder); @@ -361,6 +392,32 @@ Decode3RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, return S; } +static DecodeStatus +Decode2RUSInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, + const void *Decoder) { + unsigned Op1, Op2, Op3; + DecodeStatus S = Decode3OpInstruction(Insn, Op1, Op2, Op3); + if (S == MCDisassembler::Success) { + DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); + DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); + Inst.addOperand(MCOperand::CreateImm(Op3)); + } + return S; +} + +static DecodeStatus +Decode2RUSBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, + const void *Decoder) { + unsigned Op1, Op2, Op3; + DecodeStatus S = Decode3OpInstruction(Insn, Op1, Op2, Op3); + if (S == MCDisassembler::Success) { + DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); + DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); + DecodeBitpOperand(Inst, Op3, Address, Decoder); + } + return S; +} + MCDisassembler::DecodeStatus XCoreDisassembler::getInstruction(MCInst &instr, uint64_t &Size, |