diff options
| author | Richard Osborne <richard@xmos.com> | 2013-01-27 22:28:30 +0000 |
|---|---|---|
| committer | Richard Osborne <richard@xmos.com> | 2013-01-27 22:28:30 +0000 |
| commit | 970a479c02a418726950580e13136acd2a2dc13f (patch) | |
| tree | 21be0ccf3eb1b5b9753bfb60d01534bc776fe793 /lib/Target/XCore/Disassembler/XCoreDisassembler.cpp | |
| parent | 1cc0d5a4311c2d4bc01051561549390307b789a1 (diff) | |
[XCore] Add missing l2rus instructions.
These instructions are not targeted by the compiler but they are
needed for the MC layer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173634 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/XCore/Disassembler/XCoreDisassembler.cpp')
| -rw-r--r-- | lib/Target/XCore/Disassembler/XCoreDisassembler.cpp | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp b/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp index a94f5b9c2a..c995a9c345 100644 --- a/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp +++ b/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp @@ -449,6 +449,12 @@ DecodeL2OpInstructionFail(MCInst &Inst, unsigned Insn, uint64_t Address, case 0x12c: Inst.setOpcode(XCore::ASHR_l2rus); return DecodeL2RUSBitpInstruction(Inst, Insn, Address, Decoder); + case 0x12d: + Inst.setOpcode(XCore::OUTPW_l2rus); + return DecodeL2RUSBitpInstruction(Inst, Insn, Address, Decoder); + case 0x12e: + Inst.setOpcode(XCore::INPW_l2rus); + return DecodeL2RUSBitpInstruction(Inst, Insn, Address, Decoder); case 0x13c: Inst.setOpcode(XCore::LDAWF_l2rus); return DecodeL2RUSInstruction(Inst, Insn, Address, Decoder); |