diff options
| author | Richard Osborne <richard@xmos.com> | 2013-02-17 22:32:41 +0000 |
|---|---|---|
| committer | Richard Osborne <richard@xmos.com> | 2013-02-17 22:32:41 +0000 |
| commit | 763c858edeb76173ee4ef5ab9bf7d750db5d8c4f (patch) | |
| tree | 737b594237e940eeaccbddf6ece0babfff498b2f /lib/Target/XCore/Disassembler/XCoreDisassembler.cpp | |
| parent | a970dde9060d8994c242bd186bb3636d2caf22d2 (diff) | |
[XCore] Add TSETR instruction.
This instruction is not targeted by the compiler but it is needed for the
MC layer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175406 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/XCore/Disassembler/XCoreDisassembler.cpp')
| -rw-r--r-- | lib/Target/XCore/Disassembler/XCoreDisassembler.cpp | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp b/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp index c995a9c345..0bae15c014 100644 --- a/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp +++ b/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp @@ -140,6 +140,11 @@ static DecodeStatus Decode3RInstruction(MCInst &Inst, uint64_t Address, const void *Decoder); +static DecodeStatus Decode3RImmInstruction(MCInst &Inst, + unsigned Insn, + uint64_t Address, + const void *Decoder); + static DecodeStatus Decode2RUSInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, @@ -313,6 +318,9 @@ Decode2OpInstructionFail(MCInst &Inst, unsigned Insn, uint64_t Address, case 0x16: Inst.setOpcode(XCore::EQ_2rus); return Decode2RUSInstruction(Inst, Insn, Address, Decoder); + case 0x17: + Inst.setOpcode(XCore::TSETR_3r); + return Decode3RImmInstruction(Inst, Insn, Address, Decoder); case 0x18: Inst.setOpcode(XCore::LSS_3r); return Decode3RInstruction(Inst, Insn, Address, Decoder); @@ -516,6 +524,19 @@ Decode3RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, } static DecodeStatus +Decode3RImmInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, + const void *Decoder) { + unsigned Op1, Op2, Op3; + DecodeStatus S = Decode3OpInstruction(Insn, Op1, Op2, Op3); + if (S == MCDisassembler::Success) { + Inst.addOperand(MCOperand::CreateImm(Op1)); + DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); + DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder); + } + return S; +} + +static DecodeStatus Decode2RUSInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) { unsigned Op1, Op2, Op3; |