diff options
| author | Richard Osborne <richard@xmos.com> | 2012-12-17 13:50:04 +0000 |
|---|---|---|
| committer | Richard Osborne <richard@xmos.com> | 2012-12-17 13:50:04 +0000 |
| commit | 35150cbf4166ae8d69032d355f1e8d83b4a6eb3c (patch) | |
| tree | c2e54c7213d750760d601f6d230c784464d05993 /lib/Target/XCore/Disassembler/XCoreDisassembler.cpp | |
| parent | 7f7d201d737ecb354abd683d63ab8abbf83158c3 (diff) | |
Add instruction encodings / disassembly support for rus instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170330 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/XCore/Disassembler/XCoreDisassembler.cpp')
| -rw-r--r-- | lib/Target/XCore/Disassembler/XCoreDisassembler.cpp | 66 |
1 files changed, 66 insertions, 0 deletions
diff --git a/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp b/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp index 4257944231..ebbde96d06 100644 --- a/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp +++ b/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp @@ -72,6 +72,9 @@ static DecodeStatus DecodeGRRegsRegisterClass(MCInst &Inst, uint64_t Address, const void *Decoder); +static DecodeStatus DecodeBitpOperand(MCInst &Inst, unsigned Val, + uint64_t Address, const void *Decoder); + static DecodeStatus Decode2RInstruction(MCInst &Inst, unsigned RegNo, uint64_t Address, @@ -87,6 +90,21 @@ static DecodeStatus Decode2RSrcDstInstruction(MCInst &Inst, uint64_t Address, const void *Decoder); +static DecodeStatus DecodeRUSInstruction(MCInst &Inst, + unsigned Insn, + uint64_t Address, + const void *Decoder); + +static DecodeStatus DecodeRUSBitpInstruction(MCInst &Inst, + unsigned Insn, + uint64_t Address, + const void *Decoder); + +static DecodeStatus DecodeRUSSrcDstBitpInstruction(MCInst &Inst, + unsigned Insn, + uint64_t Address, + const void *Decoder); + #include "XCoreGenDisassemblerTables.inc" static DecodeStatus DecodeGRRegsRegisterClass(MCInst &Inst, @@ -101,6 +119,17 @@ static DecodeStatus DecodeGRRegsRegisterClass(MCInst &Inst, return MCDisassembler::Success; } +static DecodeStatus DecodeBitpOperand(MCInst &Inst, unsigned Val, + uint64_t Address, const void *Decoder) { + if (Val > 11) + return MCDisassembler::Fail; + static unsigned Values[] = { + 32 /*bpw*/, 1, 2, 3, 4, 5, 6, 7, 8, 16, 24, 32 + }; + Inst.addOperand(MCOperand::CreateImm(Values[Val])); + return MCDisassembler::Success; +} + static DecodeStatus Decode2OpInstruction(unsigned Insn, unsigned &Op1, unsigned &Op2) { unsigned Combined = fieldFromInstruction(Insn, 6, 5) + @@ -152,6 +181,43 @@ Decode2RSrcDstInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, return S; } +static DecodeStatus +DecodeRUSInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, + const void *Decoder) { + unsigned Op1, Op2; + DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2); + if (S == MCDisassembler::Success) { + DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); + Inst.addOperand(MCOperand::CreateImm(Op2)); + } + return S; +} + +static DecodeStatus +DecodeRUSBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, + const void *Decoder) { + unsigned Op1, Op2; + DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2); + if (S == MCDisassembler::Success) { + DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); + DecodeBitpOperand(Inst, Op2, Address, Decoder); + } + return S; +} + +static DecodeStatus +DecodeRUSSrcDstBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, + const void *Decoder) { + unsigned Op1, Op2; + DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2); + if (S == MCDisassembler::Success) { + DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); + DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); + DecodeBitpOperand(Inst, Op2, Address, Decoder); + } + return S; +} + MCDisassembler::DecodeStatus XCoreDisassembler::getInstruction(MCInst &instr, uint64_t &Size, |