diff options
| author | Richard Osborne <richard@xmos.com> | 2012-12-17 12:29:31 +0000 |
|---|---|---|
| committer | Richard Osborne <richard@xmos.com> | 2012-12-17 12:29:31 +0000 |
| commit | 1ffe48a84b398e8cebbdc7a47bedb57e1e67e63f (patch) | |
| tree | a020a503df18b88f6a91b16cc5a306b2acbffcd4 /lib/Target/XCore/Disassembler/XCoreDisassembler.cpp | |
| parent | dd78daa199f653b64b997fdee46db8964e5c50cc (diff) | |
Add instruction encodings / disassembly support for 2r instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170323 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/XCore/Disassembler/XCoreDisassembler.cpp')
| -rw-r--r-- | lib/Target/XCore/Disassembler/XCoreDisassembler.cpp | 67 |
1 files changed, 66 insertions, 1 deletions
diff --git a/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp b/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp index 16b91d996c..4257944231 100644 --- a/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp +++ b/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp @@ -67,12 +67,26 @@ static unsigned getReg(const void *D, unsigned RC, unsigned RegNo) { return *(Dis->getRegInfo()->getRegClass(RC).begin() + RegNo); } - static DecodeStatus DecodeGRRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder); +static DecodeStatus Decode2RInstruction(MCInst &Inst, + unsigned RegNo, + uint64_t Address, + const void *Decoder); + +static DecodeStatus DecodeR2RInstruction(MCInst &Inst, + unsigned RegNo, + uint64_t Address, + const void *Decoder); + +static DecodeStatus Decode2RSrcDstInstruction(MCInst &Inst, + unsigned RegNo, + uint64_t Address, + const void *Decoder); + #include "XCoreGenDisassemblerTables.inc" static DecodeStatus DecodeGRRegsRegisterClass(MCInst &Inst, @@ -87,6 +101,57 @@ static DecodeStatus DecodeGRRegsRegisterClass(MCInst &Inst, return MCDisassembler::Success; } +static DecodeStatus +Decode2OpInstruction(unsigned Insn, unsigned &Op1, unsigned &Op2) { + unsigned Combined = fieldFromInstruction(Insn, 6, 5) + + fieldFromInstruction(Insn, 5, 1) * 5 - 27; + if (Combined >= 9) + return MCDisassembler::Fail; + + unsigned Op1High = Combined % 3; + unsigned Op2High = Combined / 3; + Op1 = (Op1High << 2) | fieldFromInstruction(Insn, 2, 2); + Op2 = (Op2High << 2) | fieldFromInstruction(Insn, 0, 2); + return MCDisassembler::Success; +} + +static DecodeStatus +Decode2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, + const void *Decoder) { + unsigned Op1, Op2; + DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2); + if (S == MCDisassembler::Success) { + DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); + DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); + } + return S; +} + +static DecodeStatus +DecodeR2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, + const void *Decoder) { + unsigned Op1, Op2; + DecodeStatus S = Decode2OpInstruction(Insn, Op2, Op1); + if (S == MCDisassembler::Success) { + DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); + DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); + } + return S; +} + +static DecodeStatus +Decode2RSrcDstInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, + const void *Decoder) { + unsigned Op1, Op2; + DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2); + if (S == MCDisassembler::Success) { + DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); + DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); + DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); + } + return S; +} + MCDisassembler::DecodeStatus XCoreDisassembler::getInstruction(MCInst &instr, uint64_t &Size, |