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| author | Richard Osborne <richard@xmos.com> | 2013-01-25 21:25:12 +0000 |
|---|---|---|
| committer | Richard Osborne <richard@xmos.com> | 2013-01-25 21:25:12 +0000 |
| commit | 1f375e5bc78647f9b29564eafdc907250ccd91ed (patch) | |
| tree | 7f342d9a82414c36b7a5155d48808e3e8bfbf9db /lib/Target/XCore/Disassembler/XCoreDisassembler.cpp | |
| parent | 0f1bcedf5a871c360f2ca1354464d81cb81bdca7 (diff) | |
Use the correct format in the STW / SETPSC instruction names.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173494 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/XCore/Disassembler/XCoreDisassembler.cpp')
| -rw-r--r-- | lib/Target/XCore/Disassembler/XCoreDisassembler.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp b/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp index e785030c38..821c33da51 100644 --- a/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp +++ b/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp @@ -401,7 +401,7 @@ DecodeL2OpInstructionFail(MCInst &Inst, unsigned Insn, uint64_t Address, fieldFromInstruction(Insn, 27, 5) << 4; switch (Opcode) { case 0x0c: - Inst.setOpcode(XCore::STW_3r); + Inst.setOpcode(XCore::STW_l3r); return DecodeL3RInstruction(Inst, Insn, Address, Decoder); case 0x1c: Inst.setOpcode(XCore::XOR_l3r); |