Use TableGen to emit information for dwarf register numbers.

This makes DwarfRegNum to accept list of numbers instead.
Added three different "flavours", but only slightly tested on x86-32/linux.
Please check another subtargets if possible,


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43997 91177308-0d34-0410-b5e6-96231b3b80d8

3 files changed, 136 insertions, 162 deletions

diff --git a/lib/Target/X86/X86RegisterInfo.cpp b/lib/Target/X86/X86RegisterInfo.cpp
index 1432d1306d..9d8a208c6e 100644
--- a/lib/Target/X86/X86RegisterInfo.cpp
+++ b/lib/Target/X86/X86RegisterInfo.cpp
@@ -656,58 +656,22 @@ X86RegisterInfo::X86RegisterInfo(X86TargetMachine &tm,
 
 // getDwarfRegNum - This function maps LLVM register identifiers to the
 // Dwarf specific numbering, used in debug info and exception tables.
-// The registers are given "basic" dwarf numbers in the .td files,
-// which are for the 64-bit target.  These are collected by TableGen 
-// into X86GenRegisterInfo::getDwarfRegNum and overridden here for
-// other targets.
-// FIXME:  Comments in gcc indicate that Darwin uses different numbering
-// for debug info and exception handling info:(  The numbering here is
-// for exception handling.
 
 int X86RegisterInfo::getDwarfRegNum(unsigned RegNo) const {
-  int n = X86GenRegisterInfo::getDwarfRegNum(RegNo);
   const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
+  unsigned Flavour = DWARFFlavour::X86_64;
   if (!Subtarget->is64Bit()) {
-    // Numbers are all different for 32-bit.  Further, some of them
-    // differ between Darwin and other targets.
-    switch (n) {
-    default: assert(0 && "Invalid argument to getDwarfRegNum"); 
-             return n;
-    case 0:  return 0;                              // ax
-    case 1:  return 2;                              // dx
-    case 2:  return 1;                              // cx
-    case 3:  return 3;                              // bx
-    case 4:  return 6;                              // si
-    case 5:  return 7;                              // di
-    case 6:  return (Subtarget->isDarwin) ? 4 : 5;  // bp
-    case 7:  return (Subtarget->isDarwin) ? 5 : 4;  // sp
-
-    case 8:  case 9:  case 10: case 11:             // r8..r15
-    case 12: case 13: case 14: case 15:
-      assert(0 && "Invalid register in 32-bit mode"); 
-      return n;
-
-    case 16: return 8;                              // ip
-
-    case 17: case 18: case 19: case 20:             // xmm0..xmm7  
-    case 21: case 22: case 23: case 24:  
-      return n+4;
-
-    case 25: case 26: case 27: case 28:             // xmm8..xmm15
-    case 29: case 30: case 31: case 32:
-      assert(0 && "Invalid register in 32-bit mode"); 
-      return n;
-
-    case 33: case 34: case 35: case 36:             // st0..st7
-    case 37: case 38: case 39: case 40:
-      return (Subtarget->isDarwin) ? n-21 : n-22;
-
-    case 41: case 42: case 43: case 44:             // mm0..mm7
-    case 45: case 46: case 47: case 48:
-      return n-12;
+    if (Subtarget->isTargetDarwin()) {
+      Flavour = DWARFFlavour::X86_32_Darwin;
+    } else if (Subtarget->isTargetCygMing()) {
+      // Unsupported by now, just quick fallback
+      Flavour = DWARFFlavour::X86_32_ELF;
+    } else {
+      Flavour = DWARFFlavour::X86_32_ELF;
     }
   }
-  return n;
+
+  return X86GenRegisterInfo::getDwarfRegNumFull(RegNo, Flavour);
 }
 
 // getX86RegNum - This function maps LLVM register identifiers to their X86
diff --git a/lib/Target/X86/X86RegisterInfo.h b/lib/Target/X86/X86RegisterInfo.h
index ec526c1773..30902889cf 100644
--- a/lib/Target/X86/X86RegisterInfo.h
+++ b/lib/Target/X86/X86RegisterInfo.h
@@ -32,6 +32,14 @@ namespace N86 {
   };
 }
 
+/// DWARFFlavour - Flavour of dwarf regnumbers
+///
+namespace DWARFFlavour {
+  enum {
+    X86_64 = 0, X86_32_Darwin = 1, X86_32_ELF = 2
+  };
+} 
+  
 class X86RegisterInfo : public X86GenRegisterInfo {
 public:
   X86TargetMachine &TM;
diff --git a/lib/Target/X86/X86RegisterInfo.td b/lib/Target/X86/X86RegisterInfo.td
index 4fc23a223f..9d9a14e36c 100644
--- a/lib/Target/X86/X86RegisterInfo.td
+++ b/lib/Target/X86/X86RegisterInfo.td
@@ -23,149 +23,151 @@ let Namespace = "X86" in {
   // because the register file generator is smart enough to figure out that
   // AL aliases AX if we tell it that AX aliased AL (for example).
 
-  // Dwarf numbering is different for 32-bit and 64-bit, and there are
-  // variations by target as well.  The numbers here are for 64-bit.
-  // They are altered by X86RegisterInfo::getDwarfRegNum at runtime.  Note
-  // that we can't assign the same number here to different registers, as
-  // getDwarfRegNum has only the number here to work with.
+  // Dwarf numbering is different for 32-bit and 64-bit, and there are 
+  // variations by target as well. Currently the first entry is for X86-64, 
+  // second - for X86-32/Darwin and third for X86-32/Linux
+
+  // FIXME:  Comments in gcc indicate that Darwin uses different numbering
+  // for debug info and exception handling info:(  The numbering here is
+  // for exception handling.
 
   // 8-bit registers
   // Low registers
-  def AL : Register<"AL">, DwarfRegNum<0>;
-  def DL : Register<"DL">, DwarfRegNum<1>;
-  def CL : Register<"CL">, DwarfRegNum<2>;
-  def BL : Register<"BL">, DwarfRegNum<3>;
+  def AL : Register<"AL">, DwarfRegNum<[0, 0, 0]>;
+  def DL : Register<"DL">, DwarfRegNum<[1, 2, 2]>;
+  def CL : Register<"CL">, DwarfRegNum<[2, 1, 1]>;
+  def BL : Register<"BL">, DwarfRegNum<[3, 3, 3]>;
 
   // X86-64 only
-  def SIL : Register<"SIL">, DwarfRegNum<4>;
-  def DIL : Register<"DIL">, DwarfRegNum<5>;
-  def BPL : Register<"BPL">, DwarfRegNum<6>;
-  def SPL : Register<"SPL">, DwarfRegNum<7>;
-  def R8B  : Register<"R8B">,  DwarfRegNum<8>;
-  def R9B  : Register<"R9B">,  DwarfRegNum<9>;
-  def R10B : Register<"R10B">, DwarfRegNum<10>;
-  def R11B : Register<"R11B">, DwarfRegNum<11>;
-  def R12B : Register<"R12B">, DwarfRegNum<12>;
-  def R13B : Register<"R13B">, DwarfRegNum<13>;
-  def R14B : Register<"R14B">, DwarfRegNum<14>;
-  def R15B : Register<"R15B">, DwarfRegNum<15>;
+  def SIL : Register<"SIL">, DwarfRegNum<[4, 6, 6]>;
+  def DIL : Register<"DIL">, DwarfRegNum<[5, 7, 7]>;
+  def BPL : Register<"BPL">, DwarfRegNum<[6, 4, 5]>;
+  def SPL : Register<"SPL">, DwarfRegNum<[7, 5, 4]>;
+  def R8B  : Register<"R8B">,  DwarfRegNum<[8, -2, -2]>;
+  def R9B  : Register<"R9B">,  DwarfRegNum<[9, -2, -2]>;
+  def R10B : Register<"R10B">, DwarfRegNum<[10, -2, -2]>;
+  def R11B : Register<"R11B">, DwarfRegNum<[11, -2, -2]>;
+  def R12B : Register<"R12B">, DwarfRegNum<[12, -2, -2]>;
+  def R13B : Register<"R13B">, DwarfRegNum<[13, -2, -2]>;
+  def R14B : Register<"R14B">, DwarfRegNum<[14, -2, -2]>;
+  def R15B : Register<"R15B">, DwarfRegNum<[15, -2, -2]>;
 
   // High registers X86-32 only
-  def AH : Register<"AH">, DwarfRegNum<0>;
-  def DH : Register<"DH">, DwarfRegNum<1>;
-  def CH : Register<"CH">, DwarfRegNum<2>;
-  def BH : Register<"BH">, DwarfRegNum<3>;
+  def AH : Register<"AH">, DwarfRegNum<[0, 0, 0]>;
+  def DH : Register<"DH">, DwarfRegNum<[1, 2, 2]>;
+  def CH : Register<"CH">, DwarfRegNum<[2, 1, 1]>;
+  def BH : Register<"BH">, DwarfRegNum<[3, 3, 3]>;
 
   // 16-bit registers
-  def AX : RegisterWithSubRegs<"AX", [AH,AL]>, DwarfRegNum<0>;
-  def DX : RegisterWithSubRegs<"DX", [DH,DL]>, DwarfRegNum<1>;
-  def CX : RegisterWithSubRegs<"CX", [CH,CL]>, DwarfRegNum<2>;
-  def BX : RegisterWithSubRegs<"BX", [BH,BL]>, DwarfRegNum<3>;
-  def SI : RegisterWithSubRegs<"SI", [SIL]>, DwarfRegNum<4>;
-  def DI : RegisterWithSubRegs<"DI", [DIL]>, DwarfRegNum<5>;
-  def BP : RegisterWithSubRegs<"BP", [BPL]>, DwarfRegNum<6>;
-  def SP : RegisterWithSubRegs<"SP", [SPL]>, DwarfRegNum<7>;
-  def IP : Register<"IP">, DwarfRegNum<16>;
+  def AX : RegisterWithSubRegs<"AX", [AH,AL]>, DwarfRegNum<[0, 0, 0]>;
+  def DX : RegisterWithSubRegs<"DX", [DH,DL]>, DwarfRegNum<[1, 2, 2]>;
+  def CX : RegisterWithSubRegs<"CX", [CH,CL]>, DwarfRegNum<[2, 1, 1]>;
+  def BX : RegisterWithSubRegs<"BX", [BH,BL]>, DwarfRegNum<[3, 3, 3]>;
+  def SI : RegisterWithSubRegs<"SI", [SIL]>, DwarfRegNum<[4, 6, 6]>;
+  def DI : RegisterWithSubRegs<"DI", [DIL]>, DwarfRegNum<[5, 7, 7]>;
+  def BP : RegisterWithSubRegs<"BP", [BPL]>, DwarfRegNum<[6, 4, 5]>;
+  def SP : RegisterWithSubRegs<"SP", [SPL]>, DwarfRegNum<[7, 5, 4]>;
+  def IP : Register<"IP">, DwarfRegNum<[16]>;
   
   // X86-64 only
-  def R8W  : RegisterWithSubRegs<"R8W", [R8B]>, DwarfRegNum<8>;
-  def R9W  : RegisterWithSubRegs<"R9W", [R9B]>, DwarfRegNum<9>;
-  def R10W : RegisterWithSubRegs<"R10W", [R10B]>, DwarfRegNum<10>;
-  def R11W : RegisterWithSubRegs<"R11W", [R11B]>, DwarfRegNum<11>;
-  def R12W : RegisterWithSubRegs<"R12W", [R12B]>, DwarfRegNum<12>;
-  def R13W : RegisterWithSubRegs<"R13W", [R13B]>, DwarfRegNum<13>;
-  def R14W : RegisterWithSubRegs<"R14W", [R14B]>, DwarfRegNum<14>;
-  def R15W : RegisterWithSubRegs<"R15W", [R15B]>, DwarfRegNum<15>;
+  def R8W  : RegisterWithSubRegs<"R8W", [R8B]>, DwarfRegNum<[8, -2, -2]>;
+  def R9W  : RegisterWithSubRegs<"R9W", [R9B]>, DwarfRegNum<[9, -2, -2]>;
+  def R10W : RegisterWithSubRegs<"R10W", [R10B]>, DwarfRegNum<[10, -2, -2]>;
+  def R11W : RegisterWithSubRegs<"R11W", [R11B]>, DwarfRegNum<[11, -2, -2]>;
+  def R12W : RegisterWithSubRegs<"R12W", [R12B]>, DwarfRegNum<[12, -2, -2]>;
+  def R13W : RegisterWithSubRegs<"R13W", [R13B]>, DwarfRegNum<[13, -2, -2]>;
+  def R14W : RegisterWithSubRegs<"R14W", [R14B]>, DwarfRegNum<[14, -2, -2]>;
+  def R15W : RegisterWithSubRegs<"R15W", [R15B]>, DwarfRegNum<[15, -2, -2]>;
 
   // 32-bit registers
-  def EAX : RegisterWithSubRegs<"EAX", [AX]>, DwarfRegNum<0>;
-  def EDX : RegisterWithSubRegs<"EDX", [DX]>, DwarfRegNum<1>;
-  def ECX : RegisterWithSubRegs<"ECX", [CX]>, DwarfRegNum<2>;
-  def EBX : RegisterWithSubRegs<"EBX", [BX]>, DwarfRegNum<3>;
-  def ESI : RegisterWithSubRegs<"ESI", [SI]>, DwarfRegNum<4>;
-  def EDI : RegisterWithSubRegs<"EDI", [DI]>, DwarfRegNum<5>;
-  def EBP : RegisterWithSubRegs<"EBP", [BP]>, DwarfRegNum<6>;
-  def ESP : RegisterWithSubRegs<"ESP", [SP]>, DwarfRegNum<7>;
-  def EIP : RegisterWithSubRegs<"EIP", [IP]>, DwarfRegNum<16>;  
+  def EAX : RegisterWithSubRegs<"EAX", [AX]>, DwarfRegNum<[0, 0, 0]>;
+  def EDX : RegisterWithSubRegs<"EDX", [DX]>, DwarfRegNum<[1, 2, 2]>;
+  def ECX : RegisterWithSubRegs<"ECX", [CX]>, DwarfRegNum<[2, 1, 1]>;
+  def EBX : RegisterWithSubRegs<"EBX", [BX]>, DwarfRegNum<[3, 3, 3]>;
+  def ESI : RegisterWithSubRegs<"ESI", [SI]>, DwarfRegNum<[4, 6, 6]>;
+  def EDI : RegisterWithSubRegs<"EDI", [DI]>, DwarfRegNum<[5, 7, 7]>;
+  def EBP : RegisterWithSubRegs<"EBP", [BP]>, DwarfRegNum<[6, 4, 5]>;
+  def ESP : RegisterWithSubRegs<"ESP", [SP]>, DwarfRegNum<[7, 5, 4]>;
+  def EIP : RegisterWithSubRegs<"EIP", [IP]>, DwarfRegNum<[16, 8, 8]>;  
   
   // X86-64 only
-  def R8D  : RegisterWithSubRegs<"R8D", [R8W]>, DwarfRegNum<8>;
-  def R9D  : RegisterWithSubRegs<"R9D", [R9W]>, DwarfRegNum<9>;
-  def R10D : RegisterWithSubRegs<"R10D", [R10W]>, DwarfRegNum<10>;
-  def R11D : RegisterWithSubRegs<"R11D", [R11W]>, DwarfRegNum<11>;
-  def R12D : RegisterWithSubRegs<"R12D", [R12W]>, DwarfRegNum<12>;
-  def R13D : RegisterWithSubRegs<"R13D", [R13W]>, DwarfRegNum<13>;
-  def R14D : RegisterWithSubRegs<"R14D", [R14W]>, DwarfRegNum<14>;
-  def R15D : RegisterWithSubRegs<"R15D", [R15W]>, DwarfRegNum<15>;
+  def R8D  : RegisterWithSubRegs<"R8D", [R8W]>, DwarfRegNum<[8, -2, -2]>;
+  def R9D  : RegisterWithSubRegs<"R9D", [R9W]>, DwarfRegNum<[9, -2, -2]>;
+  def R10D : RegisterWithSubRegs<"R10D", [R10W]>, DwarfRegNum<[10, -2, -2]>;
+  def R11D : RegisterWithSubRegs<"R11D", [R11W]>, DwarfRegNum<[11, -2, -2]>;
+  def R12D : RegisterWithSubRegs<"R12D", [R12W]>, DwarfRegNum<[12, -2, -2]>;
+  def R13D : RegisterWithSubRegs<"R13D", [R13W]>, DwarfRegNum<[13, -2, -2]>;
+  def R14D : RegisterWithSubRegs<"R14D", [R14W]>, DwarfRegNum<[14, -2, -2]>;
+  def R15D : RegisterWithSubRegs<"R15D", [R15W]>, DwarfRegNum<[15, -2, -2]>;
 
   // 64-bit registers, X86-64 only
-  def RAX : RegisterWithSubRegs<"RAX", [EAX]>, DwarfRegNum<0>;
-  def RDX : RegisterWithSubRegs<"RDX", [EDX]>, DwarfRegNum<1>;
-  def RCX : RegisterWithSubRegs<"RCX", [ECX]>, DwarfRegNum<2>;
-  def RBX : RegisterWithSubRegs<"RBX", [EBX]>, DwarfRegNum<3>;
-  def RSI : RegisterWithSubRegs<"RSI", [ESI]>, DwarfRegNum<4>;
-  def RDI : RegisterWithSubRegs<"RDI", [EDI]>, DwarfRegNum<5>;
-  def RBP : RegisterWithSubRegs<"RBP", [EBP]>, DwarfRegNum<6>;
-  def RSP : RegisterWithSubRegs<"RSP", [ESP]>, DwarfRegNum<7>;
-
-  def R8  : RegisterWithSubRegs<"R8", [R8D]>, DwarfRegNum<8>;
-  def R9  : RegisterWithSubRegs<"R9", [R9D]>, DwarfRegNum<9>;
-  def R10 : RegisterWithSubRegs<"R10", [R10D]>, DwarfRegNum<10>;
-  def R11 : RegisterWithSubRegs<"R11", [R11D]>, DwarfRegNum<11>;
-  def R12 : RegisterWithSubRegs<"R12", [R12D]>, DwarfRegNum<12>;
-  def R13 : RegisterWithSubRegs<"R13", [R13D]>, DwarfRegNum<13>;
-  def R14 : RegisterWithSubRegs<"R14", [R14D]>, DwarfRegNum<14>;
-  def R15 : RegisterWithSubRegs<"R15", [R15D]>, DwarfRegNum<15>;
-  def RIP : RegisterWithSubRegs<"RIP", [EIP]>,  DwarfRegNum<16>;
+  def RAX : RegisterWithSubRegs<"RAX", [EAX]>, DwarfRegNum<[0, -2, -2]>;
+  def RDX : RegisterWithSubRegs<"RDX", [EDX]>, DwarfRegNum<[1, -2, -2]>;
+  def RCX : RegisterWithSubRegs<"RCX", [ECX]>, DwarfRegNum<[2, -2, -2]>;
+  def RBX : RegisterWithSubRegs<"RBX", [EBX]>, DwarfRegNum<[3, -2, -2]>;
+  def RSI : RegisterWithSubRegs<"RSI", [ESI]>, DwarfRegNum<[4, -2, -2]>;
+  def RDI : RegisterWithSubRegs<"RDI", [EDI]>, DwarfRegNum<[5, -2, -2]>;
+  def RBP : RegisterWithSubRegs<"RBP", [EBP]>, DwarfRegNum<[6, -2, -2]>;
+  def RSP : RegisterWithSubRegs<"RSP", [ESP]>, DwarfRegNum<[7, -2, -2]>;
+
+  def R8  : RegisterWithSubRegs<"R8", [R8D]>, DwarfRegNum<[8, -2, -2]>;
+  def R9  : RegisterWithSubRegs<"R9", [R9D]>, DwarfRegNum<[9, -2, -2]>;
+  def R10 : RegisterWithSubRegs<"R10", [R10D]>, DwarfRegNum<[10, -2, -2]>;
+  def R11 : RegisterWithSubRegs<"R11", [R11D]>, DwarfRegNum<[11, -2, -2]>;
+  def R12 : RegisterWithSubRegs<"R12", [R12D]>, DwarfRegNum<[12, -2, -2]>;
+  def R13 : RegisterWithSubRegs<"R13", [R13D]>, DwarfRegNum<[13, -2, -2]>;
+  def R14 : RegisterWithSubRegs<"R14", [R14D]>, DwarfRegNum<[14, -2, -2]>;
+  def R15 : RegisterWithSubRegs<"R15", [R15D]>, DwarfRegNum<[15, -2, -2]>;
+  def RIP : RegisterWithSubRegs<"RIP", [EIP]>,  DwarfRegNum<[16, -2, -2]>;
 
   // MMX Registers. These are actually aliased to ST0 .. ST7
-  def MM0 : Register<"MM0">, DwarfRegNum<41>;
-  def MM1 : Register<"MM1">, DwarfRegNum<42>;
-  def MM2 : Register<"MM2">, DwarfRegNum<43>;
-  def MM3 : Register<"MM3">, DwarfRegNum<44>;
-  def MM4 : Register<"MM4">, DwarfRegNum<45>;
-  def MM5 : Register<"MM5">, DwarfRegNum<46>;
-  def MM6 : Register<"MM6">, DwarfRegNum<47>;
-  def MM7 : Register<"MM7">, DwarfRegNum<48>;
+  def MM0 : Register<"MM0">, DwarfRegNum<[41, 29, 29]>;
+  def MM1 : Register<"MM1">, DwarfRegNum<[42, 30, 30]>;
+  def MM2 : Register<"MM2">, DwarfRegNum<[43, 31, 31]>;
+  def MM3 : Register<"MM3">, DwarfRegNum<[44, 32, 32]>;
+  def MM4 : Register<"MM4">, DwarfRegNum<[45, 33, 33]>;
+  def MM5 : Register<"MM5">, DwarfRegNum<[46, 34, 34]>;
+  def MM6 : Register<"MM6">, DwarfRegNum<[47, 35, 35]>;
+  def MM7 : Register<"MM7">, DwarfRegNum<[48, 36, 36]>;
   
   // Pseudo Floating Point registers
-  def FP0 : Register<"FP0">, DwarfRegNum<-1>;
-  def FP1 : Register<"FP1">, DwarfRegNum<-1>;
-  def FP2 : Register<"FP2">, DwarfRegNum<-1>;
-  def FP3 : Register<"FP3">, DwarfRegNum<-1>;
-  def FP4 : Register<"FP4">, DwarfRegNum<-1>;
-  def FP5 : Register<"FP5">, DwarfRegNum<-1>;
-  def FP6 : Register<"FP6">, DwarfRegNum<-1>; 
+  def FP0 : Register<"FP0">;
+  def FP1 : Register<"FP1">;
+  def FP2 : Register<"FP2">;
+  def FP3 : Register<"FP3">;
+  def FP4 : Register<"FP4">;
+  def FP5 : Register<"FP5">;
+  def FP6 : Register<"FP6">; 
 
   // XMM Registers, used by the various SSE instruction set extensions
-  def XMM0: Register<"XMM0">, DwarfRegNum<17>;
-  def XMM1: Register<"XMM1">, DwarfRegNum<18>;
-  def XMM2: Register<"XMM2">, DwarfRegNum<19>;
-  def XMM3: Register<"XMM3">, DwarfRegNum<20>;
-  def XMM4: Register<"XMM4">, DwarfRegNum<21>;
-  def XMM5: Register<"XMM5">, DwarfRegNum<22>;
-  def XMM6: Register<"XMM6">, DwarfRegNum<23>;
-  def XMM7: Register<"XMM7">, DwarfRegNum<24>;
+  def XMM0: Register<"XMM0">, DwarfRegNum<[17, 21, 21]>;
+  def XMM1: Register<"XMM1">, DwarfRegNum<[18, 22, 22]>;
+  def XMM2: Register<"XMM2">, DwarfRegNum<[19, 23, 23]>;
+  def XMM3: Register<"XMM3">, DwarfRegNum<[20, 24, 24]>;
+  def XMM4: Register<"XMM4">, DwarfRegNum<[21, 25, 25]>;
+  def XMM5: Register<"XMM5">, DwarfRegNum<[22, 26, 26]>;
+  def XMM6: Register<"XMM6">, DwarfRegNum<[23, 27, 27]>;
+  def XMM7: Register<"XMM7">, DwarfRegNum<[24, 28, 28]>;
 
   // X86-64 only
-  def XMM8:  Register<"XMM8">,  DwarfRegNum<25>;
-  def XMM9:  Register<"XMM9">,  DwarfRegNum<26>;
-  def XMM10: Register<"XMM10">, DwarfRegNum<27>;
-  def XMM11: Register<"XMM11">, DwarfRegNum<28>;
-  def XMM12: Register<"XMM12">, DwarfRegNum<29>;
-  def XMM13: Register<"XMM13">, DwarfRegNum<30>;
-  def XMM14: Register<"XMM14">, DwarfRegNum<31>;
-  def XMM15: Register<"XMM15">, DwarfRegNum<32>;
+  def XMM8:  Register<"XMM8">,  DwarfRegNum<[25, -2, -2]>;
+  def XMM9:  Register<"XMM9">,  DwarfRegNum<[26, -2, -2]>;
+  def XMM10: Register<"XMM10">, DwarfRegNum<[27, -2, -2]>;
+  def XMM11: Register<"XMM11">, DwarfRegNum<[28, -2, -2]>;
+  def XMM12: Register<"XMM12">, DwarfRegNum<[29, -2, -2]>;
+  def XMM13: Register<"XMM13">, DwarfRegNum<[30, -2, -2]>;
+  def XMM14: Register<"XMM14">, DwarfRegNum<[31, -2, -2]>;
+  def XMM15: Register<"XMM15">, DwarfRegNum<[32, -2, -2]>;
 
   // Floating point stack registers
-  def ST0 : Register<"ST(0)">, DwarfRegNum<33>;
-  def ST1 : Register<"ST(1)">, DwarfRegNum<34>;
-  def ST2 : Register<"ST(2)">, DwarfRegNum<35>;
-  def ST3 : Register<"ST(3)">, DwarfRegNum<36>;
-  def ST4 : Register<"ST(4)">, DwarfRegNum<37>;
-  def ST5 : Register<"ST(5)">, DwarfRegNum<38>;
-  def ST6 : Register<"ST(6)">, DwarfRegNum<39>;
-  def ST7 : Register<"ST(7)">, DwarfRegNum<40>; 
+  def ST0 : Register<"ST(0)">, DwarfRegNum<[33, 12, 11]>;
+  def ST1 : Register<"ST(1)">, DwarfRegNum<[34, 13, 12]>;
+  def ST2 : Register<"ST(2)">, DwarfRegNum<[35, 14, 13]>;
+  def ST3 : Register<"ST(3)">, DwarfRegNum<[36, 15, 14]>;
+  def ST4 : Register<"ST(4)">, DwarfRegNum<[37, 16, 15]>;
+  def ST5 : Register<"ST(5)">, DwarfRegNum<[38, 17, 16]>;
+  def ST6 : Register<"ST(6)">, DwarfRegNum<[39, 18, 17]>;
+  def ST7 : Register<"ST(7)">, DwarfRegNum<[40, 19, 18]>; 
 
   // Status flags register
   def EFLAGS : Register<"EFLAGS">;