Rework the SelectionDAG-based implementations of SimplifyDemandedBits

and ComputeMaskedBits to match the new improved versions in instcombine.
Tested against all of multisource/benchmarks on ppc.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26238 91177308-0d34-0410-b5e6-96231b3b80d8

1 files changed, 9 insertions, 5 deletions

diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp
index adaa986ffc..3e0a21063f 100644
--- a/lib/Target/X86/X86ISelLowering.cpp
+++ b/lib/Target/X86/X86ISelLowering.cpp
@@ -2035,19 +2035,23 @@ const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
   }
 }
 
-bool X86TargetLowering::isMaskedValueZeroForTargetNode(const SDOperand &Op,
-                                                       uint64_t Mask) const {
+void X86TargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op,
+                                                       uint64_t Mask,
+                                                       uint64_t &KnownZero, 
+                                                       uint64_t &KnownOne,
+                                                       unsigned Depth) const {
 
   unsigned Opc = Op.getOpcode();
+  KnownZero = KnownOne = 0;   // Don't know anything.
 
   switch (Opc) {
   default:
     assert(Opc >= ISD::BUILTIN_OP_END && "Expected a target specific node");
     break;
-  case X86ISD::SETCC: return (Mask & 1) == 0;
+  case X86ISD::SETCC: 
+    KnownZero |= (MVT::getIntVTBitMask(Op.getValueType()) ^ 1ULL);
+    break;
   }
-
-  return false;
 }
 
 std::vector<unsigned> X86TargetLowering::